Intel Corporation

Ncr Corporation

Larry C James

Gene F Young

Roy M Stevens

David L Simpson

Peter Washington

Chris A Harrison

Mark A Taylor

Edward A McDonald

Thomas F Heil

Arthur F Cochcroft, Jr

Billy K Taylor

Jeffrey A Hawkey

Thomas Edward Stonecypher, Jr

Jeffrey F Gates

Carl W Kagy

Method and apparatus for using one bit per line of system memory to maintain coherency in a dual-ported memory system. The states of the bit are 'Owned' and 'Unowned.' The state of the bit is used to filter the number of cycles required to maintain coherency. The bits are stored within the system memory.

Directory-based coherency system for maintaining coherency in a

Memory controller logic for concurrently obtaining memory access locality information by cycle type for a large number of contiguous sections of system memory (pages) for the purposes of optimizing memory and process assignments in a multiple-node NUMA architecture computer system including a distributed system memory. Page access monitoring logic is included within each processing node which contains a portion of shared system memory. This page access monitoring logic maintains a plurality of page access counters, each page access counter corresponding to a different memory page address within the shared system memory. The monitoring logic further includes a programmable cycle control register and comparison logic to condition the page access counters for specific memory cycle types, such as coherency cycles, reads, writes, copyback cache cycles, etc. Whenever the processing node generates a transaction requiring access to a memory address within system memory which matches the cycle type specified in the cycle control register, the page access monitoring logic increments a count value contained within the page access counter corresponding to the memory address to which access is sought. Thus, a record of memory access patterns by cycle type is created which can be used to optimize memory and process assignments in the computer system.

Method and apparatus for monitoring bus transactions based on cycle type

A method implemented in hardware to concurrently obtain memory access locality information for a large number of contiguous sections of system memory (pages) for the purposes of optimizing memory and process assignments in a multiple-node NUMA architecture computer system including a distributed system memory. Page access monitoring logic is included within each processing node which contains a portion of shared system memory. This page access monitoring logic maintains a plurality of page access counters, each page access counter corresponding to a different memory page address within the shared system memory. Whenever the processing node generates a transaction requiring access to a memory address within system memory, the page access monitoring logic increments a count value contained within the page access counter corresponding to the memory address to which access is sought. Each processing node further includes page access counter search logic connected to the plurality of page access counters, which is enabled upon completion of page access monitoring, for sequentially comparing the contents of each page access counter with a predetermined minimum count value to identify the page access counters having contents equal to or greater than the minimum count value, and to identify the memory page addresses associated with the page access counters having contents equal to or greater than the minimum count value. This information can thereafter be used to optimize memory and process assignments in the computer system.

Method and apparatus for determining memory pages having greatest

A method, implemented in hardware, to successively obtain memory access locality information for a large number of contiguous sections of system memory (pages) for the purposes of optimizing memory and process assignments in a multiple-node NUMA architecture computer system including a distributed system memory. Page access monitoring logic is included within each processing node which contains a portion of shared system memory. This page access monitoring logic maintains a plurality of page access counters, each page access counter corresponding to a different memory page address within a specified address range within system memory. Whenever the processing node generates a transaction requiring access to a memory address within the specified address range, the page access monitoring logic increments a count value contained within the page access counter corresponding to the memory address to which access is sought. The specified address range is defined by an address value contained within a range counter. The range counter is initially loaded with a starting address value, defining a first group of page addresses to monitor. This address value is periodically incremented up to a preset maximum address value to define successive groups of page addresses to be monitored. Thus, a record of memory access patterns to successive portions of system memory is created which can be used to optimize memory and process assignments in the computer system.

Method and apparatus for dynamically monitoring memory page access

A hardware method to concurrently obtain memory access locality information for a large number of contiguous sections of system memory (pages) for the purposes of optimizing memory and process assignments in a multiple-node NUMA architecture computer system including a distributed system memory. Page access monitoring logic is included within each processing node which contains a portion of shared system memory. This page access monitoring logic maintains a plurality of page access counters, each page access counter corresponding to a different memory page address within the shared system memory. Whenever the processing node generates a transaction requiring access to a memory address within system memory, the page access monitoring logic increments a count value contained within the page access counter corresponding to the memory address to which access is sought. Thus, a record of memory access patterns is created which can be used to optimize memory and process assignments in the computer system.

Method and apparatus for determining memory page access information in a

An improved directory-based cache coherency memory system for a multiprocessor computer system. The memory system includes a dual ported system memory shared by the multiple processors within the computer system; a plurality of data cache memories, at least one data cache memory associated with each processor; and first and second memory busses, the first memory bus connecting a first subset of processors and associated data cache memories to a first port (PORT A) of the system memory, and the second memory bus connecting a second subset of processors and associated data cache memories to a second port (PORT B) of the system memory. Cache coherency is maintained through the use of memory line state information saved with each line of memory within the system memory and data cache memories. The system memory contains a system memory line state for each line of memory saved within the system memory, the system memory line state being any one of the group: SHARED PORT A, SHARED BOTH, OWNED PORT A and OWNED PORT B. Each one of these states is represented by a different two bit code saved with each line of memory in system memory. Additionally, each data cache memory contains a data cache memory line state for each line of memory saved within the data cache memory, the data cache memory line state being any one of the group: MODIFIED, EXCLUSIVE, SHARED, or INVALID.

Directory-based coherency system using two bits to maintain coherency on

A directory-based cache coherency memory system for a multiprocessor computer system. The memory system includes a system memory shared by the multiple processors within the computer system; a plurality of data cache memories, at least one data cache memory associated with each processor; a system of busses interconnecting the system memory with the plurality of data cache memories and processors, and a state cache memory associated with the shared system memory for the storage of memory line state information identifying where within the system memory and the plurality of data cache memories the most current copy of a line of memory resides. The state cache memory is sized to store state information for only a portion of the memory lines included in system memory, e.g., one sixteenth of the memory lines contained in system memory, in recognition that rarely will all of system memory be utilized (cached) at any one time. The state cache can be a direct mapped cache wherein state information for an associated line of memory is stored within the state cache together with a tag field being a first portion of the address of the associated line of memory, and indexed within the state cache by the remaining portion of the address.

Method and apparatus for caching state information within a

An improved method for performing state cache line replacement operations in a multiprocessor computer system including plurality if data cache memories, a shared system memory, a state cache memory, and employing a centralized/distributed directory-based cache coherency system for maintaining consistency between lines of memory within the shared system memory and the plurality of data cache memories. The method for performing state cache line replacement operations includes the steps of: establishing a default system memory line state of SHARED for lines of memory represented in said state cache memory; reading the system memory line state for a previously stored state cache entry prior to a replacement of said previously stored state cache entry, said previously stored state cache entry being associated with a line of memory stored in said shared memory and at least one data cache memory; and performing a castout operation to update the line of memory within said shared memory and assigning a data cache memory line state of SHARED to said line of memory in each data cache memory containing said line of memory if said system memory line state for said previously stored state cache entry is OWNED. Since most lines of memory are in a shared state prior to replacement, setting the default state to a shared state, rather than a uncached state, reduces the number of invalidate coherency operations which must be performed during state cache line replacements.

Method for reducing the number of coherency cycles within a

Intermodule testing in a computer system including a plurality of modules interconnected via a system bus is performed by means of a serial test bus which is incorporated into the computer system for testing components, for example integrated circuits, used to construct the modules of the computer system. Intermodule test data is maintained in memory on each of the modules and is accessible through operations of the serial test bus. Intermodule test data is retrieved by the serial test bus and used to set up the modules so that one module drives the system bus with test signals defined by test vectors included within the intermodule test data. The remaining modules are set up to receive the test signals. Tables are developed in accordance with the intermodule test data to define which test signals drive which system bus leads and also which receiving modules receive the test signals. The signals which are received by the modules set up to receive the test signals are sampled and compared to what signals should have been received to detect errors in intermodule communications. The selection of the module used to drive the system bus is rotated until all modules have driven the system bus.

Intermodule test across system bus utilizing serial test bus

System configuration, monitoring and control functions are performed in a computer system by means of a serial test bus which is incorporated into the computer system for testing components, for example integrated circuits, used to construct one or more modules of the system. The conventional serial test bus is modified to include register circuitry on modules of the computer system and/or within integrated circuits which are interconnected to construct the modules. These registers are written and read by the serial test bus for configuring the computer system as well as performing other operations such as monitoring and error logging within the computer system. To extend the amount of information which can be contained within these registers, preferably memory devices such as EEPROM, RAM, and the like, are associated with the registers and accessible therethrough. The introduction of memory into the serial test bus permits configuration information to be stored in the modules and/or integrated circuits making up the computer system. If memory and/or other devices external to the serial test bus are included on modules or other components of the system, the time required to access these devices may exceed a default access time defined by the operating speed of the serial test bus. To ensure proper operation with such devices, a pacing or ready signal is generated such that access is delayed until the requested access can be successfully completed.

Computer system configuration via test bus

Nonvolatile memory is provided on each module of a computer system including one or more modules with each module including a plurality of components including JTAG technology. A test bus operable in accordance with the 1149.1 standard is included in the computer system and is arranged to access the nonvolatile memory. Boundary scan information for the components on a module and also additional information, preferably fully describing all JTAG related characteristics and operations, is stored in the nonvolatile memory. A JTAG bus system is then able to access the module memory and obtain all information required to fully implement JTAG operations for the module.

JTAG component description via nonvolatile memory

A memory device is disclosed which is comprised of a plurality of memory boards each having at least one memory bank associated therewith with each memory bank including a plurality of memory elements addressable by rows and columns. In page-mode operation of the memory device, all of the memory elements receive the active row address strobe signal RAS. The RAS signal is maintained active as long as the memory is to remain in page-mode operation. Memory address information is decoded to select a memory board and a memory bank from the plurality of memory boards and to enable the memory elements to permit either a read or a write operation without the need for performing additional address strobe cycles.

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West Columbia, SC, United States of America

Larry C James