Silicon Graphics, Incorporated

Mips Computer Systems, Inc.

Larry B Weber

Earl A Killian

Mark I Himelstein

Thomas J Riordan

Craig C Hansen

Steven A Przybylski

A method and computer program-product for converting a program designed to be executed on a computer system employing a first predefined memory order, such as the Big Endian architecture, to a program which is executable on a computer system employing a second predefined memory order, such as the Little Endian architecture. The method and computer program-product uses the fact that performing a logical operation on the lower two bits of a byte address in one architecture converts that byte address to the equivalent byte address in the other architecture. The method and computer program-product are implemented in software by scanning the instructions of the input for load and store instructions. The software modifies the instructions by taking the contents of the register and operating on the two least significant bits of the byte address with a logical operation to generate two complementary bits used to replace the two least significant bits of the byte address to generate a new byte address that corresponds with the other architecture.

System and method for obtaining correct byte addresses by using logical

A method and apparatus for enabling a computer to run using either a Big Endian or Little Endian architecture is provided. The method and apparatus use the fact that XORing the lower two bits of a byte address in one architecture with a binary 3 converts that byte address to the equivalent byte address in the other architecture. The conversion method and apparatus is implemented in hardware by setting a bit in a status register indicating a Big Endian or Little Endian architecture in conjunction with an XOR gate which couples the byte address to binary 3. The conversion method and apparatus is implemented in software by scanning the instructions of the input for load and store instructions. The software modifies the instructions by taking the contents of the register and XORing the two least significant bits of the byte address with a binary 3.

System for obtaining correct byte addresses by XOR-ING 2 LSB bits of

A CPU or other function unit is disclosed which follows one data ordering scheme internally, and in which incoming and/or outgoing data pass through a data order conversion unit for adapting it to a selectable external data ordering scheme. The means for specifying the external data ordering scheme is accessible from outside the physical package(s) in which the functional unit is housed. The data order conversion unit may comprise a load aligner and/or a store aligner, one or both of which may comprise means for shifting informational units of a smaller size within informational units of a larger size. The shift amount may derive from the low order address bits and may be altered depending on the external data ordering means selected.

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Palo Alto, CA, United States of America

Larry B Weber