Nxp Usa, Inc.

Advanced Micro Devices Corporation

Larry Alan Woodrum

Carl Culshaw

Jehoda Refaeli

Martin Mienkina

Rajiv M Hattangadi

Nancy Hing-Che Amedeo

Ashwin I Matta

David Eromosele

A processing system including processors, peripheral slots, hardware resources, and gateway circuitry. Each processor is assigned a corresponding identifier. The peripheral slots are located within an addressable peripheral space. Each hardware resource is placed into a corresponding peripheral slot, including at least one direct memory access (DMA) device supporting at least one DMA channel and at least one general-purpose input/output (GPIO) pin. Memory protection and gateway circuitry is programmed to control access of the hardware resources only by a processor that provides a matching identifier. The memories along with hardware resources are protected against unauthorized accesses to isolate applications executed on each processor within a multicore system and hence support freedom of interference.

System and method of limiting access of processors to hardware resources

A data processing system and methods for operating the same are disclosed. The method includes detecting a fault by comparing output signals from a first processing core and a second processing core, entering a safe mode based upon detecting the fault, completing transactions while in the safe mode, and determining whether the fault corresponds to a hard error. Based upon the fault corresponding to a hard error, one of processing cores is identified as a faulty core. The faulty core is inhibited from executing instructions and the other processing core is allowed to execute instructions.

Data processing system having lockstep operation

A method is herein provided for placing drivers and repeaters along the interconnect so as to optimize interconnection propagation delay with respect to area and time constraints. The method provided optimizes the propagation delay and simplifies the propagation delay determination by first using drivers to divide an interconnect into forkless branches, then linearizing the delay of each branch by placing repeaters along the length of the branches.

Method for optimization of multi-level interconnect RC delay

Growing community of inventors

Austin, TX, United States of America

Larry Alan Woodrum