International Business Machines Corporation

Other

Infineon Technologies Ag

Qimonda Ag

Larry Alan Nesbit

Charles W Koburger, Iii

David V Horak

Mark Charles Hakey

Steven J Holmes

Toshiharu Furukawa

Peter H Mitchell

Ramachandra Divakaruni

Jack Allan Mandelman

Carl John Radens

Rama Divakaruni

Gary Bela Bronner

Ulrike Gruening

Wolfgang Bergner

Jeffrey P Gambino

Jerome Brett Lasky

Rajeev Malik

Lawrence Alfred Clevenger

Helmut Horst Tews

James Albert Slinkman

Jochen C Beintner

Johnathan E Faltermeier

Henry J Geipel, Jr

Wayne I Kinney

Rolf Weis

Till Schloesser

Byeong Yeol Kim

David M Dobuzinsky

Stephan Kudelka

Chienfan Yu

Francis Roger White

Jeremy K Stephens

Munir D Naeem

Alexander Michaelis

Scott R Stiffler

Ronald R Troutman

Larry Clevenger

Irene Lennox McStay

George C Feng

Michael Maldei

Thomas O Sedgwick

John R Abernathey

Prakash Chimanlal Dev

Ning Hsieh

Kia Seng Low

Stephen Kudelka

David Vaclav Hotak

David Vaclav Hofak

Jonathan E Faltermeier

David Vaclav Horak

Steven John Holmes

Charles William Iii Koburger

Ulrike Grüning

A method for fabricating a metal-oxide-semiconductor device structure. The method includes introducing a dopant species concurrently into a semiconductor active layer that overlies an insulating layer and a gate electrode overlying the semiconductor active layer by ion implantation. The thickness of the semiconductor active layer, the thickness of the gate electrode, and the kinetic energy of the dopant species are chosen such that the projected range of the dopant species in the semiconductor active layer and insulating layer lies within the insulating layer and a projected range of the dopant species in the gate electrode lies within the gate electrode. As a result, the semiconductor active layer and the gate electrode may be doped simultaneously during a single ion implantation and without the necessity of an additional implant mask.

Metal-oxide-semiconductor device structures with tailored dopant depth profiles

Methods for fabricating a metal-oxide-semiconductor device structure

A trench-type storage device includes a trench in a substrate (), with bundles of carbon nanotubes () lining the trench and a trench conductor () filling the trench. A trench dielectric () may be formed between the carbon nanotubes and the sidewall of the trench. The bundles of carbon nanotubes form an open cylinder structure lining the trench. The device is formed by providing a carbon nanotube catalyst structure on the substrate and patterning the trench in the substrate; the carbon nanotubes are then grown down into the trench to line the trench with the carbon nanotube bundles, after which the trench is filled with the trench conductor.

Carbon nanotube conductor for trench capacitors

Methods for synthesizing carbon nanotubes and structures formed thereby, includes forming carbon nanotubes on a plurality of synthesis sites supported by a first substrate, interrupting nanotube synthesis, mounting a free end of each carbon nanotube to a second substrate, and removing the first substrate. Each carbon nanotube is capped by one of the synthesis sites, to which growth reactants have ready access.

Methods and structures for promoting stable synthesis of carbon nanotubes

Carbon nanotube field effect transistors, arrays of carbon nanotube field effect transistors, device structures, and arrays of device structures. A stacked device structure includes a gate electrode layer and catalyst pads each coupled electrically with a source/drain contact. The gate electrode layer is divided into multiple gate electrodes and at least one semiconducting carbon nanotube is synthesized by a chemical vapor deposition process on each of the catalyst pads. The gate electrode has a sidewall covered by a gate dielectric and at least one semiconducting carbon nanotube adjacent to the sidewall of the gate electrode. Source/drain contacts are electrically coupled with opposite ends of the semiconducting carbon nanotube to complete the device structure. Multiple device structures may be configured either as a memory circuit or as a logic circuit.

Vertical carbon nanotube field effect transistors and arrays

A method for forming carbon nanotube field effect transistors, arrays of carbon nanotube field effect transistors, and device structures and arrays of device structures formed by the methods. The methods include forming a stacked structure including a gate electrode layer and catalyst pads each coupled electrically with a source/drain contact. The gate electrode layer is divided into multiple gate electrodes and at least one semiconducting carbon nanotube is synthesized by a chemical vapor deposition process on each of the catalyst pads. The completed device structure includes a gate electrode with a sidewall covered by a gate dielectric and at least one semiconducting carbon nanotube adjacent to the sidewall of the gate electrode. Source/drain contacts are electrically coupled with opposite ends of the semiconducting carbon nanotube to complete the device structure. Multiple device structures may be configured either as a memory circuit or as a logic circuit.

Methods of fabricating vertical carbon nanotube field effect transistors for arrangement in arrays and field effect transistors and arrays formed thereby

Vertical device structures incorporating at least one nanotube and methods for fabricating such device structures by chemical vapor deposition. Each nanotube is grown by chemical vapor deposition catalyzed by a catalyst pad and encased in a coating of a dielectric material. Vertical field effect transistors may be fashioned by forming a gate electrode about the encased nanotubes such that the encased nanotubes extend vertically through the thickness of the gate electrode. Capacitors may be fashioned in which the encased nanotubes and the corresponding catalyst pad bearing the encased nanotubes forms one capacitor plate.

Vertical nanotube semiconductor device structures and methods of forming the same

A method of patterning which provides images substantially smaller than that possible by lithographic techniques is provided. In the method of the invention, a substrate has a memory layer and a sacrificial layer formed thereon. An image is patterned onto the memory layer by protecting an edge during an etching step using chemical oxide removal (COR) processes, for example. Another edge is memorized in the layer. The sacrificial layer is removed to expose another memorized edge, which is used to define a pattern in an underlying layer.

Sub-lithographic imaging techniques and processes

To isolate two active regions formed on a silicon-on-insulator (SOI) substrate, a shallow trench isolation region is filled with liquid phase deposited silicon dioxide (LPD-SiO) while avoiding covering the active areas with the oxide. By selectively depositing the oxide in this manner, the polishing needed to planarize the wafer is significantly reduced as compared to a chemical-vapor deposited oxide layer that covers the entire wafer surface. Additionally, the LPD-SiOdoes not include the growth seams that CVD silicon dioxide does. Accordingly, the etch rate of the LPD-SiOis uniform across its entire expanse thereby preventing cavities and other etching irregularities present in prior art shallow trench isolation regions in which the etch rate of growth seams exceeds that of the other oxide areas.

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The invention relates generally to a method for fabricating oxygen-implanted semiconductors, and more particularly to a method for fabricating oxygen-implanted silicon-on-insulation ('SOI') type semiconductors by cutting-up regions into device-sized pieces prior to the SOI-oxidation process. The process sequence to make SOI is modified so that the implant dose may be reduced and relatively long and high temperature annealing process steps may be shortened or eliminated. This simplification may be achieved if, after oxygen implant, the wafer structure is sent to pad formation, and masking and etching. After the etching, annealing or oxidation process steps may be performed to create the SOI wafer.

Method for fabricating oxygen-implanted silicon on insulation type semiconductor and semiconductor formed therefrom

Sublithographic contact apertures through a dielectric are formed in a stack of dielectric, hardmask and oxide-containing seed layer. An initial aperture through the seed layer receives a deposition of oxide by liquid phase deposition, which adheres selectively to the exposed vertical walls of the aperture in the seed layer. The sublithographic aperture, reduced in size by the thickness of the added material, defines a reduced aperture in the hardmask. The reduced hardmask then defines the sublithographic aperture through the dielectric.

Shrinking contact apertures through LPD oxide

A method for synthesizing carbon nanotubes and structure formed thereby. The method includes forming carbon nanotubes on a plurality of synthesis sites supported by a first substrate, interrupting nanotube synthesis, mounting a free end of each carbon nanotube to a second substrate, and removing the first substrate. Each carbon nanotube is capped by one of the synthesis sites, to which growth reactants have ready access. As the carbon nanotubes lengthen during resumed nanotube synthesis, access to the synthesis sites remains unoccluded.

Vertical field effect transistors having a channel region defined by at least one semiconducting nanotube and methods for fabricating such vertical field effect transistors by chemical vapor deposition using a spacer-defined channel. Each nanotube is grown by chemical vapor deposition catalyzed by a catalyst pad positioned at the base of a high-aspect-ratio passage defined between a spacer and a gate electrode. Each nanotube grows in the passage with a vertical orientation constrained by the confining presence of the spacer. A gap may be provided in the base of the spacer remote from the mouth of the passage. Reactants flowing through the gap to the catalyst pad participate in nanotube growth.

Vertical field effect transistors incorporating semiconducting nanotubes grown in a spacer-defined passage

Shallow trench isolation fill by liquid phase deposition of SiO2

Methods for fabricating alternating phase shift masks or reticles used in semiconductor optical lithography systems. The methods generally include forming a layer of phase shift mask material on a handle substrate and patterning the layer to define recessed phase shift windows. The patterned layer is transferred from the handle wafer to a mask blank. The depth of the phase shift windows is determined by the thickness of the layer of phase shift mask material and is independent of the patterning process. In particular, the depth of the phase shift windows is not dependent upon the etch rate uniformity of an etch process across a surface of a mask blank.

Methods of forming alternating phase shift masks having improved phase-shift tolerance

Growing community of inventors

Williston, VT, United States of America

Larry Alan Nesbit