Ramtron International Corporation

Texas Instruments Corporation

Chaologix, Inc.

Lark E Lehman

William F Kraus

Dennis R Wilson

Judith E Allen

Steven D Traynor

Francis B Frazee

James H Cline

Mark Adrian Bryans

Michael J Schneiderwind

Douglas N Krening

Steven Lee Kiel

A dynamically configurable logic gate includes an input summer for receiving a first input signal and a second input signal to generate a summed input signal. Further the dynamically configurable logic gate includes a nonlinear element that applies a nonlinear function to the summed input signal to produce a nonlinear output signal. The dynamically configurable logic gate output signal corresponds to one of a plurality of different logic gates responsive to adjusting the summed input signal and/or the nonlinear function. In another embodiment, the dynamically configurable logic gate includes feedback to one of the inputs. The dynamically configurable logic gate receives the two inputs and operates as one of a plurality of different logic gate types so as to produce an output signal that corresponds to a memory latch according to a selection of the control signal. An array structure of dynamically configurable logic elements is also disclosed.

Dynamically configurable logic gate using a non-linear element

A memory cell layout for use in a 1T/1C ferroelectric memory array includes an access transistor having a gate coupled to a word line and a current path coupled between a bit line and an internal cell node, a shunt word line extending across the memory cell that is electrically isolated from the word line and the access transistor within the physical boundary of the memory cell, and a ferroelectric capacitor coupled between the internal cell node and a plate line.

Sense amplifier configuration for a 1T/1C ferroelectric memory

A memory cell layout for use in a,T/,C ferroelectric memory array includes an access transistor having a gate coupled to a word line and a current path coupled between a bit line and an internal cell node, a shunt word line extending across the memory cell that is electrically isolated from the word line and the access transistor within the physical boundary of the memory cell, and a ferroelectric capacitor coupled between the internal cell node and a plate line.

Reference cell configuration for a 1T/1C ferroelectric memory

Memory cell configuration for a 1T/1C ferroelectric memory

A plate line segmentation scheme for a 1T/1C ferroelectric memory architecture includes an array of 1T/1C ferroelectric memory cells, word lines corresponding to each row of 1T/1C ferroelectric memory cells, and plate lines corresponding to each row of 1T/1C ferroelectric memory cells, wherein each plate line is divided into two or more equal plate line segments, only one of which is driven when a corresponding word line is selected.

Plate line segmentation in a 1T/1C ferroelectric memory

A reference cell layout for use in a 1T/1C ferroelectric memory array includes a transistor of a first polarity type having a gate coupled to a reference word line and a current path coupled between a bit line and an internal cell node, a transistor of a second polarity type having a gate coupled to a pre-charge line and a current path coupled between a source of power supply voltage and the internal cell node, a shunt reference word line extending across the reference cell that is electrically isolated from the reference word line, the pre-charge line and the transistors within the physical boundary of the memory cell, and a ferroelectric capacitor coupled between the internal cell node and a reference plate line.

A sense amplifier cell layout for use in a 1T/1C ferroelectric memory array includes a first sense amplifier having two input/output nodes for receiving a first bit line signal and a first inverted bit line signal and a second sense amplifier having two input/output nodes for receiving a second bit line signal and a second inverted bit line signal, wherein the combined width of the first and second sense amplifiers is substantially the same as the width of two columns of 1T/1C memory cells used in the array.

A reference cell for a 1T/1C ferroelectric memory includes a transistor of a first polarity type having a gate coupled to a reference cell word line, and a current path coupled between a bit line and an internal reference cell node, a transistor of a second polarity type having a gate coupled to a pre-charge line, and a current path coupled between a source of supply voltage and the internal reference cell node, and a ferroelectric capacitor coupled between the internal reference cell node and ground.

Reference cell for a 1T/1C ferroelectric memory

A method of operating a 1T/1C ferroelectric memory having a memory cell coupled to a word line, a bit line, and a plate line, includes the steps of turning on the word line, energizing the plate line to establish a charge on the bit line, turning off the word line, and sensing the charge on the bit line while the word line is off.

Sensing methodology for a 1T/1C ferroelectric memory

A high bit-rate serial communications link encodes data by inserting non-data 0's and 1's. These extra bits are removed by a decoder at the receiving end of the link. Transmission of data can be made along optical fibers.

Growing community of inventors

Colorado Springs, CO, United States of America

Lark E Lehman