Chartered Semiconductor Manufacturing Ltd (corporation)

Other

National University of Singapore

Globalfoundries Singapore Pte. Ltd.

Nanyang Technological University

Asm Technology Singapore Pte Ltd

Institute of Microelectronics

National Univ. of Singapore

Nanyang Technology Univ.

Nahyang Techn. Univ. of Singapore

Chartered Semiconductor Manu. Ltd.

Chartered Semiconductors Manufactured Limited

Lap Chan

Jia Zhen Zheng

Yelehanka Ramachandramurthy Pradeep

Yang Pan

Ravi Sundaresan

Elgin Kiok Quek

Ying Keung Leung

James Yong Meng Lee

Cher Liang Cha

Alex See

Purakh Raj Verma

Sanford Chu

Randall Cher Liang Cha

Kheng Chok Tee

Kin Leong Pey

Shao-fu Sanford Chu

Ting Cheong Ang

Jian Xun Li

Chee Tee Chua

Che-Chia Wei

Chit Hwei Ng

Tae Jong Lee

Hou Tee Ng

Simon Yew-Meng Chooi

Yung Fu Chong

Feng Chen

Kok Keng Ong

Mei Sheng Zhou

Ravishankar Sundaresan

Shyue Fong Quek

Sang Yee Loong

Yeow Kheng Lim

Kiat Seng Yeo

Yeow Meng Teo

Manh Anh Do

Sai Hooi Yeong

Suh Fei Lim

Choi Pheng Soo

Teck Koon Lee

Wye Boon Loh

Benjamin Colombeau

Pooi See Lee

Jun Song

Francis Lionel Benistant

Chaw Sing Ho

Wang Ling Goh

Kai Shao

Victor Seng Keong Lim

Sam Fong Yau Li

Kok Wai Chew

Kok Wai Johnny Chew

Bangun Indajang

Johnny Kok Wai Chew

Eng Fong Chor

Kok Hin Teo

James Yongmeng Lee

Wai Kin Chim

Chee Chong Lim

Shyue Pong Quek

Bob Hsino-Lun Lee

Jiazhen Zheng

Johnny Chew

Choon Beng Sia

Poh Suan Tan

Wee Kiong Choi

Vivian Ng

John Leonard Sudijono

Elgin Kiok Boone Quek

Yong Meng Lee

Wei Lu

Lee Wee Teo

Soh Yun Siah

Yong Kong Siew

Ganesh S Samudra

Chirn Chye Boon

Yihong Wu

Randall Cha

Pavel Neuzil

Chong Wee Lim

Sia Choon Beng

Si Liang Lu

Chock Hing Gan

Kin-Leong Pey

Vincent Ho

Harianto Wong

Fang Hong Gn

Chen Feng

Ng Chit Hwei

Chua Chee Tee

Yong Ju

Kuang Kian Ong

Peter Hing

Teng Hock Eric Kuah

Yeo Kiat Seng

Wei Hua Tong

Qinghua Zhong

Feng Dai

Lay Cheng Choo

Siew Yong Kong

Ze Xiang Shen

A transistor which includes halo regions disposed in a substrate adjacent to opposing sides of the gate. The halo regions have upper and lower regions. The upper region is a crystalline region with excess vacancies and the lower region is an amorphous region. Source/drain diffusion regions are disposed in the halo regions. The source/drain diffusion regions overlap the upper and lower halo regions. This architecture offers the minimal extension resistance as well as minimum lateral diffusion for better CMOS device scaling.

Method for fabricating semiconductor devices with reduced junction diffusion

Embodiments of the invention provide a transformer comprising: a first coil element having a transverse axis along a transverse direction, the first coil element having p turns where p is greater than or equal to 1; and a second coil element having a transverse axis generally parallel to the transverse axis of the first coil element, the second coil element having n turns, where n is greater than or equal to 5p; wherein the first and second coil elements are arranged to provide electromagnetic coupling between the coil elements along a portion of a length of the second coil element in both a transverse direction parallel to the transverse axes and a lateral direction, wherein the lateral direction is a direction normal to the transverse axes.

Transformer with effective high turn ratio

An inductor circuit with high quality (Q) factor includes a primary inductor and a compensation sub-circuit. The compensation sub-circuit is electrically isolated from the primary inductor. The compensation sub-circuit is magnetically coupled with the primary inductor to compensate the loss in the primary inductor.

Tunable high quality factor inductor

Formation of metal pipes resulting from formation of metal silicide contacts are reduced or avoided. To reduce formation of metal pipes, an epitaxial layer is formed over the diffusion region on which the metal silicide contact is formed. The epitaxial layer reduces defects which enhances diffusion of metal atoms or molecules.

Reduced metal pipe formation in metal silicide contacts

A method of forming an integrated circuit structure on a substrate, the substrate includes a primary region and a secondary region. A first layer of a first material of a first thickness is formed over the substrate. A portion of the first layer is removed over the primary region to expose the substrate. The structure is exposed to an oxidizing medium. This forms a second layer, for example, of an oxide material primary region of the substrate. The second layer has a second thickness. Additionally, at least a portion of said first layer is converted to a third layer, for example, of an oxynitride material. The third layer has a third thickness.

Method of forming a gate stack structure

A method for forming a shallow junction region in a crystalline semiconductor substrate and method for fabricating a semiconductor device having the shallow junction region includes a defect engineering step in which first ions are introduced into a first region of the substrate and vacancies are generated in the first region. During the generation of substrate vacancies, the first region remains substantially crystalline. Interstitial species are generated in a second region and second ions are introduced into the second region to capture the interstitial species. Laser annealing is used to activate dopant species in the first region and repair implantation damage in the second region. The defect engineering process creates a vacancy-rich surface region in which source and drain extension regions having high dopant activation and low sheet resistance are created in an MOS device.

Method for forming a shallow junction region using defect engineering and laser annealing

A molding system for provided which is configured for molding a substrate comprising a plurality of individual carriers each of which is pre-cut into a shape of a memory card device and connected to a frame of the substrate by narrow tie bars. A molding plate is configured to receive the substrate, and a cavity plate configured to be clamped to the molding plate further comprises a plurality of molding cavities each constructed in the shape of the said carriers. The cavities are operative to create molded packages onto the carrier conforming to a shape of the memory card device without need for further forming of the molded compound after molding. Additionally, a nozzle on the surface of each cavity is operative to introduce molding material into the cavity in a direction that is substantially perpendicular to a plane of the substrate placed on the molding plate.

Memory card molding apparatus and process

A new method is provided for creating an inductor on the surface of a silicon substrate. The invention provides overlying layers of oxide fins beneath a metal inductor. The oxide fins provide the stability support for the overlying metal inductor while also allowing horizontal air columns to simultaneously exist underneath the inductor. Overlying layers of air cavities that are spatially inserted between the created overlying layers of oxide fins can be created under the invention by repetitive application of the mask used. The presence of the air wells on the surface of the substrate significantly reduces parasitic capacitances and series resistance of the inductor associated with the substrate.

Method to fabricate horizontal air columns underneath metal inductor

An integrated transformer structure includes a first coil element associated with a transverse axis, the first coil element having at least one turn. The first coil element includes a first portion provided on a first lateral level, and a second portion provided on a second lateral level. The first and second lateral levels being mutually spaced apart along said transverse axis. The first and second portions being displaced laterally from said axis by different respective distances. At least one crossover portion of the first coil element, in which the first coil element being configured to provide a conducting path through at least a portion of the first portion of the first coil element to the crossover portion, through the crossover portion and subsequently through at least a portion of the second portion of the first coil element, in which any change of flow direction along said path is less than 90&#xb0; in a lateral direction.

Integrated transformer and method of fabrication thereof

A CMOS RF device and a method to fabricate said device with low gate contact resistance are described. Conventional MOS transistor is first formed with isolation regions, poly-silicon gate structure, sidewall spacers around poly gate, and implanted source/drain with lightly and heavily doped regions. A silicon dioxide layer such as TEOS is deposited, planarized with chemical mechanical polishing (CMP) to expose the gate and treated with dilute HF etchant to recess the silicon dioxide layer below the surface of the gate. Silicon nitride is then deposited and planarized with CMP and then etched except around the gates, using a oversize poly-silicon gate mask. Inter-level dielectric mask is then deposited, contact holes etched, and contact metal is deposited to form the transistor. During contact hole etch over poly-silicon gate, silicon nitride around the poly gate acts as an etch stop. Resulting structure with direct gate contact achieves significantly reduced gate resistance and thereby improved noise performance at high frequency operation, increased unit power gain frequency (f), and reduced gate delay.

MOSFET device with low gate contact resistance

A trial semiconductor photomask design having discontinuity points is provided, and each of the discontinuity points is treated as simulated light sources. Simulated light from each of the simulated light sources is focused, and a composite image intensity of the focused simulated light is calculated to verify the trial semiconductor photomask design. The trial semiconductor photomask design is sharpened. A photomask design specification is generated for use in fabricating such a photomask.

System and method for designing semiconductor photomasks

A first method of reducing semiconductor device substrate effects comprising the following steps. Oor Oare selectively implanted into a silicon substrate to form a silicon-damaged silicon oxide region. One or more devices are formed over the silicon substrate proximate the silicon-damaged silicon oxide region within at least one upper dielectric layer. A passivation layer is formed over the at least one upper dielectric layer. The passivation layer and the at least one upper dielectric layer are patterned to form a trench exposing a portion of the silicon substrate over the silicon-damaged silicon oxide region. The silicon-damaged silicon oxide region is selectively etched to form a channel continuous and contiguous with the trench whereby the channel reduces the substrate effects of the one or more semiconductor devices. A second method of reducing substrate effects under analog devices includes forming an analog device on a SOI substrate and then selectively etching the silicon oxide layer of the SOI substrate to form a channel at least partially underlying the analog device.

Process to reduce substrate effects by forming channels under inductor devices and around analog blocks

A lateral heterojunction bipolar transistor (HBT) comprising a semiconductor substrate having having a first insulating layer over the semiconductor substrate. A base trench is formed in a first silicon layer over the first insulating layer to form a collector layer over an exposed portion of the semiconductor substrate and an emitter layer over the first insulating layer. A semiconductive layer is formed on the sidewalls of the base trench to form a collector structure in contact with the collector layer and an emitter structure in contact with the emitter layer. A base structure is formed in the base trench. A plurality of connections is formed through an interlevel dielectric layer to the collector layer, the emitter layer, and the base structure. The base structure preferably is a compound semiconductive material of silicon and at least one of silicon-germanium, silicon-germanium-carbon, and combinations thereof.

Self-aligned lateral heterojunction bipolar transistor

The invention provides a new multilevel interconnect structure of air gaps in a layer of IMD. A first layer of dielectric is provided over a surface; the surface contains metal points of contact. Trenches are provided in this first layer of dielectric. The trenches are filled with a first layer of nitride or disposable solid and polished. A second layer of dielectric is deposited over the first layer of dielectric. Trenches are formed in the second layer of dielectric, a second layer of nitride or disposable solid is deposited over the second layer of dielectric. The layer of nitride or disposable solid is polished. A thin layer of oxide is deposited over the surface of the second layer of dielectric. The thin layer of oxide is masked and etched thereby creating openings in this thin layer of oxide, these openings align with the points of intersect of the trenches in the first layer of dielectric and in the second layer of dielectric. The nitride or removable solid is removed from the trenches. The openings in the thin layer of oxide are closed off leaving a network of trenches that are filled with air in the two layers of dielectric that now function as the Inter Level Dielectric.

Method to form a cross network of air gaps within IMD layer

Growing community of inventors

Singapore, Singapore

Lap Chan