Motorola Corporation

Other

General Dynamics C4 Systems, Inc.

Lansing M Carson

Robert J Burdge

Robert A Frosch

Neil Evan Welter

Dean J Boman

James William Startup

Richard A Bienz

F Elvin Krasin

Marty K Siemon

Stephen Chi Humg Ma

A system () and method for the reception and despreading of a code-division multiple access (CDMA) global positioning system (GPS) signal (), or other direct-sequence spread-spectrum (DSSS) signals, is provided. An antenna array () receives the DSSS signal () over a plurality of elements (). A preprocessor () down converts and digitizes the DSSS signal () to produce a signal stream () in the time domain. An FFT () transforms the signal stream () to the frequency domain. A beam former () generates a reception beam () for the DSSS signal () in the frequency domain, and also implements a narrowband frequency notch, if desired. A despreader () despreads the transformed signal stream () in the frequency domain. An IFFT () transforms the despread signal stream () back to the time domain. And a postprocessor () converts the transformed despread signal stream () into a desired received signal stream () in the time domain.

System and method for the directional reception and despreading of direct-sequence spread-spectrum signals

A multichannel time shared demodulator (10) is implemented in an efficient ASIC architecture that provides routing-of user voice channels and access channels to a collection of time-shared processors for rapid signal detection, tracking and demodulation. The channels are routed in a random order and then processed by a time-shared symbol synchronization processor (18) for voice channels and a time-shared detection processor for access channels. The signals are over-sampled via a time-shared interpolation filter. The interpolation process yields a ten to one over sampling ration of all signals. A synchronized clock is used to choose the phases of the interpolation filter outputs.

Multichannel time shared demodulator and method

A data communication receiver (10) uses a decision feedback demodulator (32) to remove data from a received signal. Quadrature components of the received signal define a received phase. The received phase is rotated (46) by an amount predicted to compensate for phase and frequency errors. After this rotation, a decision circuit (52) determines the modulation phase for a current symbol. A phase rotator (64) compares the modulation phase with the received phase to generate a measured phase error for the symbol. This measured phase error and measured phase errors from past symbols are averaged in a combination circuit (80) to produce a phase estimate. The past measured phase errors are also processed to determine the amount of change in measured phase error that has occurred over a number of symbols. This processing yields a frequency estimate. A phase rotator (94) merges the frequency and phase estimates for use in compensating a current received phase.

Decision feedback demodulator with phase and frequency estimation

A bit error estimator produces a count of detected errors in a TDMA burst data radio transmission. An input phase signal is translated into one of a number of quadrants. A feedback phase estimator then averages the difference between the input phase signal and an output phase signal in a feedback loop to determine an average of the signal differences. The bit error rate estimator then produces a pseudo error count over a predefined time period which is proportional to the number and magnitude of any bit errors in the TDMA burst data radio transmission.

Bit error rate estimator

A digital single sideband modulator (10) includes a relatively complex CMOS NCO (14) that drives a relatively simple ECL frequency translator (30). The frequency translator (30) outputs a digital signal that is converted to analog by a D/A (44) and then filtered in a bandpass filter (46) having a pass band including a frequency of twice the NCO's clock frequency. The NCO (14) generates a modulated intermediate frequency NCO signal having quadrature components. The frequency translator (30) multiplies real and imaginary components of the NCO signal by real and imaginary components of digitized SIN, COS sampling functions (48, 50). The resulting products are added together. The adding operation is performed by a multiplexer (32), whose selection input is driven at twice the carrier frequency, and the multiplying operations are performed by a selective negation circuit (34), that is driven at the carrier frequency.

Digital single sideband modulator and method

A transponder demodulates a phase modulated ranging signal transmitted by an earth station. The transponder converts the analog ranging signal to digital form. The digital ranging signal is demodulated into its I and Q phase components. Next the demodulated ranging signal is re-modulated and digitally combined with a selected transmit frequency. Then the re-modulated ranging signal is converted from digital to analog form. The ranging signal is transmitted to the earth station.

Digital range turn-around for tracking, telemetry and control transponder

A method and apparatus for generating two phase-coherent first and second signals with arbitrary frequency ratio includes programming a first numerically controlled oscillator (NCO) with a first frequency word to produce a first NCO output. The first NCO output is processed to produce the first signal. The first frequency word is multiplied in a multiplier to produce a second frequency word which is corrected in phase relative to the first frequency word. A second NCO is programmed with the corrected second frequency word to produce a second NCO output. The second NCO output is processed to produce the second signal.

Method and apparatus for generating two phase-coherent signals with

A method for multiplexing a series of frequency division multiple access (FDMA) signals includes providing complex channels offset relative to the FDMA signals. Each FDMA signal is filtered to be centered and occupy one-half of the bandwidth of each complex channel, leaving an 'off' channel between each pair of successive FDMA signals. The real part of the multiplexed output signal is processed and higher frequency signals of FDMA signals image into the 'off' channels. Demultiplexing includes aligning a demultiplexing channelization pattern with the multiplexed input signal contained in input channels. The input channels are one-half a bandwidth of each of the complex channels. The input channels contain a sequence of FDMA signals separated by a reverse sequence of images of the FDMA signals. Consecutive even-numbered input channels correspond to consecutive complex channels of the complex channels and the sequence of FDMA signals can be extracted from the complex channels.

Method for FDMA signal multiplexing and demultiplexing

A coherent transponder having a transmitter and a receiver operating at different frequencies with each including a numerically controlled oscillator for controlling the frequency thereof through a single-sideband modulator and various outputs from a phase-locked loop the frequencies of the numerically controlled oscillators and the phase-locked loop being referenced to a single crystal controlled oscillator.

Simplified frequency scheme for coherent transponders

A discriminator aided technique for acquisition of phase lock to a suppressed carrier signal utilizes a Costas loop which is initially operated open loop and control voltage for its VCXO is derived from a phase detector that compares the VCXO to a reference frequency thus establishing coarse frequency resolution with the received signal. Then the Costas loop is closed with the low-pass filter of the channel having a bandwidth much greater (by a factor of about 10) than in the I channel so that a frequency discriminator effect results to aid carrier resolution. Finally, after carrier acquisition, the Q-channel filter of the Costas loop is switched to a bandwidth substantially equal to that of the I-channel for carrier tracking.

Discriminator aided phase lock acquisition for suppressed carrier signals

In a delay-lock one-delta (.+-.1/2 chip) dithered PN code tracking loop, an indication of lock in the PN code tracking loop is provided by delaying the dithered local PN code by a half chip to produce a +0, -1 dithered PN code that is then multiplied with the received PN-spread IF signal to produce a signal proportional to the correlation of this dithered code offset from the received code. The correlation signal is bandpass filtered, amplified with AGC control, and square-law detected to obtain a DC signal proportional to the degree of correlation. The DC signal is multiplied by the dithering control signal to effectively subtract noise voltage from the lock correlation signal which is then compared with a PN lock status signal.

PN Lock indicator for dithered PN code tracking loop

A dual bandwidth loop filter includes a filter loop, resistive means, switching means for coupling and decoupling the resistive means for changing the bandwidth of the loop from a wider acquisition bandwidth to a narrower tracking bandwidth and a sweep generator for enabling the filter to provide sweep acquisition of an incoming signal.

Dual bandwidth loop filter with sweep generator

An automatic gain control (hereinafter referred to as AGC) circuitry is used in conjunction with a Costas loop detector to provide positive gain control during the acquisition and tracking modes of the operation of a receiver. The circuitry includes circuitry for deriving a noise estimate signal from one channel of the Costas loop and circuitry for subtracting the noise estimate signal from the data and noise signal combination in the other channel of the Costas loop for providing the automatic gain control signal to prevent false locking.

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Chandler, AZ, United States of America

Lansing M Carson