Brooktree Corporation

Hughes Aircraft Company

Pairgain Technologies, Inc.

Lewyn Consulting, Inc.

American Hospital Supply Corporation

Siliconix Incorporated

Lanny L. Lewyn

Lanny L Lewyn

Charles H Lucas

Perry Wyan Lou

Glen David Simpson

A first stage circuit for a pipeline ADC first stage combines the functions of an input sample-and-hold-plus-amplifier (SHA) stage, and the functions of the first analog-to-digital conversion stage of an ADC, including a multiplying DAC (MDAC), stage-flash ADC (SFADC) comparators, and residue opamp (RAMP). The ADC first stage is duplicated, inputs and outputs are connected, and an autozero circuit using a switched-capacitor filter feedback loop controls the RAMP bias circuitry to reduce 1/f noise and DC offsets. The sampling capacitors may be connected to the ADC input for one full sample clock time period and are disconnected from the analog input period before connecting the sampling capacitors to an amplifier voltage output or voltage reference, thereby sampling the input and allowing sufficient time for the SFADC comparators to resolve and control the MDAC capacitor settings with a low metastability error rate.

ADC first stage combining both sample-hold and ADC first stage analog-to-digital conversion functions

A monolithic integrated circuit amplifier has a gain stage and a buffer stage. The buffer stage includes an output stage and two separate voltage supplies, the second of which has a greater magnitude than the first. Switching circuitry is included that is connected to the output stage via a regulator bus. When an output demand voltage is less than a switch-over threshold, current to the output stage is provided substantially from the first voltage supply; when the output demand voltage is greater than the switch-over threshold, current to the output stage is provided substantially from the second voltage supply. Collector voltage at the output stage is dynamically controlled to be greater than the emitter voltage by a difference voltage that increases proportionally as output voltage increases above the switch-over threshold. This difference voltage is commonly referred to as &ldquo;headroom.&rdquo; The dynamic headroom control circuitry preferably includes means for predictably setting and controlling the headroom voltage at switch-over and smoothly increasing the headroom voltage up to maximum output voltage.

Multiple-voltage supply power amplifier with dynamic headroom control

In its broadest terms, the invention is an electrostatically shielded and resistively insulated high-value resistor that is implemented using a CMOS resistive sealing layer of a larger CMOS device. In particular, the IC resistor according to the invention uses a substantially continuous, resistive layer to electrically connect the resistor input and output electrodes, which are formed as portions of a top metal layer. The resistive layer itself forms a resistive electrical path between the input and output, isolation of the resistor from other components on the same integrated circuit being provided without patterning of the resistive layer. An output ring portion of the top metal layer is electrically connected to the output electrode and surrounds the input electrode. A grounded shield ring portion of the top metal layer is also preferably included. The shield ring surrounds the output ring portion and forms a first electrostatic shield for the resistor. The input and output electrodes are preferably connected to external circuitry by stacked vias that extend down to a lower metal layer, portions of which form input and output leads to external circuitry. A grounded intermediate metal layer is then preferably also included. This intermediate layer extends between the input connection and the output ring portion to form a second electrostatic shield between the input connection and the output ring portion. The invention also encompasses an integrated circuit (IC) amplifier that has the IC resistor in a feedback path.

High-value integrated circuit resistor

A digital-to-analog converter (DAC) includes separate converter segments for converting the most significant bits (MSB's) and next-most-significant bits (NSB's) of a digital input word. The MSB's are converted in a thermometer-encoded capacitive DAC (CDAC), in which the MSB's are decoded and used to control the state of CDAC switches, which connect any of a plurality of CADC reference voltages, through respective unit capacitors, to the DAC output. The NSB's are converted in a preferably binary encoded resistive DAC (RDAC), in which two separate sets (&ldquo;A&rdquo; and &ldquo;B&rdquo;) of RDAC switches selectively connect a plurality of RDAC reference voltages to respective A and B RDAC output buses. Control circuitry is included to decode and apply the MSB's as state control signals to the CDAC switches on each clock cycle. The NSB's are also decoded and applied as control signals, but on alternate clock cycles, to the A and B RDAC switch sets. Bus selection circuitry is included to select which of the A or B RDAC output buses is connected to the system output, via an RDAC output capacitor. The RDAC output thus alternates between the A and B RDAC switch sets, thereby ensuring that each set of switches will have time to settle before it is allowed to influence the output. Least significant bits (LSB's) (selected as a lower significance portion of the NSB's) are preferably separately converted in an LSB RDAC that has the same structure, control circuitry, and alternating control pattern, as the NSB, but with a down-scaling output capacitor. The DAC according to the invention thereby provides a high conversion rate with very low glitch disturbances.

Digital-to-analog converter with high-speed output

A plurality of intermediate driving devices are included in stages between a clock generator and a bank of synchronous logic devices. The outputs of the intermediate devices in each stage are connected in parallel over a wide linear dimension. The timing delay of each circuit is then subject to a small variation depending on the irregularities associated with the device characteristics used in its construction. The outputs of the intermediate devices in each stage are tied together to restore regularity and uniformity to all clock generation circuit outputs.

Uniform clock timing circuit

A monolithic integrated circuit amplifier has a gain stage and a buffer stage. The buffer stage includes an output stage and two separate voltage supplies, the second of which has a greater magnitude than the first. Switching circuitry is included that is connected to the output stage via a regulator bus. When an output demand voltage is less than a switch-over threshold, current to the output stage is provided substantially entirely from the first voltage supply; when the output demand voltage is greater than the switch-over threshold, current to the output stage is provided substantially entirely from the second voltage supply. Collector voltage at the output stage can be maintained greater than the emitter voltage by a predetermined, substantially constant amount. Voltage headroom circuitry is preferably also included for setting a voltage headroom, that is, the lowest voltage constantly available at the second current terminal of the output transistor relative to the first current terminal of the output transistor.

High efficiency power amplifier

The invention provides a stable voltage reference circuit that has a single reference diode junction. Two separate current sources are switched so as to alternately apply a first and second current to the junction, with the second current being larger than the first. The voltage over the junction thereby alternates between a first AC input voltage (V,) that has a positive temperature dependence (dV,/dT) and a second AC input voltage (V,) that has a negative temperature dependence (dV,/dT). Combining circuitry is included for adding the first and second input voltages and for thereby generating an output voltage (Vref) substantially constant with absolute temperature. The combining circuitry preferably includes an amplifier that has, for the first input voltage, a gain substantially equal to the ratio of the negative temperature dependence divided by the positive temperature dependence. The amplifier is preferably implemented as an AC amplifier, with input and feedback elements that include a monolithic capacitor network.

Stable voltage reference circuit

A flash converter is preceded by an accurate continuous-time error amplifier operating on the difference between the input signal and a feedback DAC. The DAC output is operatively coupled to the amplifier input virtual ground or summing node through, for example, a set of precision capacitors. The input circuit is also coupled to the amplifier input through a continuous-time element such as a set of precision capacitors, approximately equal in capacitance to those coupled to the DAC. The amplifier may have a moderate closed-loop forward gain such as 16 with a high-pass characteristic beyond, for example, 10 Hz. The DAC is controlled by the latched output of a digital signal processing block, which uses digital outputs from the flash converter and the last latched output to predict the next value of the input signal. Converter control loop stability is afforded by providing a lowpass character to the prediction circuit. The converter produces a digital result by adding the digital value produced by the flash, properly scaled, to the current digital output value of the digital latch driving the DAC. The digital result may be sub-sampled at any arbitrary phase of the input sampling clock to permit optimum-phase data recovery.

Recursive multi-bit ADC with predictor

The magnitudes of an input voltage and individual ones of progressive fractions of a reference voltage are compared to produce first and second output voltages. Each of the elements in a first logical network receives the first output voltage from an individual one of the comparators and the second output voltage from a comparator non-consecutive with (preferably 2 comparators removed from) such individual comparator. Signals from these elements pass to latches. The latches have assertion and negation outputs which pass to elements in a second logical network. When an individual one of the elements in the second logical network provides a particular output, it prevents the elements receiving outputs from comparators responsive to lower reference voltage fractions from providing the particular output. When an element in the second logical network responsive to a latch with a higher reference voltage fraction provides an output within a preset time, its output supersedes that of the lower individual element and prevents all lower elements in such logical network from responding. In this way, only the element in the second logical network responsive to the highest reference voltage fraction within the preset time provides an output after the latches are rendered non-transparent by a second clocking signal. Elements in the second logical network are strobed by a third clocking signal at a later preset time to indicate the input voltage magnitude.

Error correcting decoder

A circuit for charging a lithium-ion battery and a technique for charging the battery are described. The battery charger takes into account the electrical series resistance (ESR) of the battery. The charger contains a compensation circuit which outputs the battery terminal voltage minus the expected voltage drop across the ESR of the battery. This resulting voltage is then applied to the sense terminals of the power supply. The voltage applied to the sense terminals of the power supply is, thus, representative of the active electrode voltage (AEV) of the battery. The power supply then provides sufficient charging current to maintain the voltage at the sense terminals at a preset voltage limit. Using this technique, the lithium-ion battery is charged to within 99.5% of its full charge in about half of the time required by the prior art.

Rapid charging technique for lithium ion batteries

Binary bits of least binary significance are converted to a corresponding analog output. Binary bits of increased binary significance are converted to a first plurality of thermometer outputs. A plurality of switching assemblies, each preferably recursive and preferably formed from a plurality of switches (e.g. transistors), process individual pairs of successive ones of such thermometer outputs. Each stage respectively produces first or second outputs or the analog output for first, second and third relationships between the thermometer outputs in such pair. The analog output has a variable value between the first and second outputs depending upon the value of the least significant binary bits. When the binary value is represented only by the binary bits of least and increased binary significance, the first, second and analog outputs are combined to produce an analog output representative of such binary bits. When the binary value additionally includes binary bits of even greater binary significance, an additional decoder decodes such binary bits to produce a second plurality of thermometer outputs. Second pluralities of switching assemblies, each plurality preferably having a construction corresponding to that of the first plurality, receive individual pairs of the thermometer outputs in the second plurality and produce the first or second outputs or an individual one of the outputs in the first plurality. These thermometer outputs are combined to produce an analog output representative of all of the binary bits. The second pluralities of switching assemblies comprise a number corresponding to the number of thermometer outputs in the second plurality.

Digital-to-analog converter with binary coded inputs to produce a

A first switch (e.g. semiconductor) becomes conductive when at least one of two binary inputs to be added is a binary '1'. A second switch (e.g. semiconductor) becomes conductive when there is a carry of a binary '1' from a preceding stage. The semiconductors provide a particular potential on an output line when both semiconductors are conductive. This potential provides a binary carry to a carry switch in the next stage. The carry switch in the next stage is an n-channel semiconductor when the carry switch in the previous stage is a p-channel semiconductor. A logical network also produces a signal when both of the binary inputs are a binary '1'. This signal causes a third switch (e.g. semiconductor) to become conductive and to produce the particular voltage on the output line whether or not the particular voltage is produced on the output line by the operation of the first and second switches. The voltage on the output line is thereafter reset to a second particular value by a reset signal from a fourth switch (e.g. semiconductor). A fifth switch (e.g. semiconductor) also simultaneously receives a reset voltage to reset the common node between the first and second switches to the particular value. The first and second switches in the next state then respectively respond to a binary '1' in at least one of two binary inputs and to the carry output from the preceding stage in the manner described above.

Binary carry circuitry

A positive energizing voltage, preferably in a CMOS circuit, is converted, primarily by a pair of buffer capacitors and secondarily by a filter capacitor, to a particular negative potential. One buffer capacitor is charged through first switches by the positive voltage during the positive half cycles of a clock signal. The buffer capacitor is discharged to a load during the negative half cycles of the clock signal through a circuit including such buffer capacitor, second switches, a third switch, a reference voltage (e.g. ground) line and a line for providing a negative biasing potential. The other buffer capacitor is charged through fourth switches by the positive voltage during the negative half cycles of the clock signals. This buffer capacitor is discharged to the load during the positive half cycles of the clock signals through a circuit including such other buffer capacitor, fifth switches, the third switch, the reference voltage line and the negative potential line. The third switch has at each instant a variable state of conductivity dependent upon the magnitude of the negative biasing potential at that instant. The magnitude of the negative potential is varied in accordance with the variations in the state of conductivity of the third switch to regulate the negative potential at a particular value. The filter capacitor is charged by the negative biasing potential and is discharged to the load when the second and fifth switches are simultaneously open. This occurs for a brief interval every time that the polarity of the clock signal changes.

Constant-current integrated power supply

A balanced cascode current mirror includes first and second current paths respectively defined by first and second transistors and by third and fourth transistors. Each current path may include the sources and drains of the transistors in such path. Connections may respectively extend between the gates of the first and third transistors and between the gates of the second and fourth transistors to provide the first and third transistors with substantially identical source, gate, and drain impedances. An input current is introduced to the drain of the second transistor and an output current with substantially identical characteristics is obtained from the drain of the fourth transistor. A capacitance may be connected between the drain of the second transistor and the gate of the first transistor to produce a flow of current at high frequencies through the first current path corresponding to the input current at the drain of the second transistor. A fifth transistor may be connected in a circuit with a constant current source to regulate the current through the first and second transistors to be substantially equal to the input current at low frequencies. The gate of the fifth transistor may be connected to the drain of the second transistor, and the source of the fifth transistor may be connected to the gate of the first transistor, to provide this current regulation. The gates of the second and fourth transistors and the drain of the fifth transistor may have a common reference potential such as ground.

Balanced cascode current mirror

A first film disposed in a first direction on an integrated circuit chip and having uniformly spaced taps provides progressively increasing resistance values. A second film disposed on the chip in a direction opposite to the first direction at a position displaced in any direction from the first film may have a construction corresponding to that of the first film. First and second reference voltages may be respectively applied to the first and second ends of the first and second films. Particular taps on the first film may be connected to taps in corresponding positions on the second film with corresponding voltages. A plurality of differential comparators are provided, each with a signal input and a reference input. Each comparator reference input is connected to an individual one of the taps on the first film, but not necessarily to successive taps. The reference input connections to the taps may have a non-linear (e.g. a luminance) spacing in the first direction to provide a non-linear voltage (e.g. a luminance) relationship between such taps. For low voltages, however, the reference input connections to the taps may have a linear spacing in the first direction to provide a linear voltage relationship between such taps. An input voltage is applied to the signal input of all the comparators. Binary signals representative of the input voltage are produced by the comparator in which the input voltage is substantially equal to the reference input voltage introduced to such comparator.

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Laguna Beach, CA, United States of America

Lanny L Lewyn