Cisco Technology, Inc.

Lane Bryon Quibodeaux

Douglas E Duschatko

Andrew J Thurston

Robert A Hall

Ali Najib Saleh

Rudolph B Klecka

David D Wilson

A frame timing adjustment apparatus is disclosed. The apparatus includes an ingress framing unit, an egress framing unit coupled to the ingress framing unit, and a framing control unit coupled to control the ingress framing unit and the egress framing unit. The ingress framing unit is configured to generate an adjusted frame by virtue of being configured to adjust a position of information within a frame. The egress framing unit is configured to frame on the adjusted frame. The framing control unit is coupled to control the ingress framing unit to generate the adjusted frame and the egress framing unit to frame the adjusted frame.

Method and apparatus for errorless frame timing adjustment

A method, apparatus and system are disclosed that more efficiently maps data into standard SONET concatenated payloads for transmission over established SONET networks. Framing information is added to a data stream to identify the beginning and ending locations of a payload. Next, the framed data stream is formatted into a non-standard STS-Nc packet. Two or more non-standard STS-Nc packets are combined to form a pseudo-standard STS-Nc packet that is supported by the established SONET network. According to one embodiment, a one Gbps Ethernet packet is framed using HDLC formatting, then formatted into an STS-24packet. Two STS-24packets are combined to form a pseudo-standard STS-48packet. In addition, the one Gbps Ethernet packet can be stored and retimed to the SONET data rate and transmitted across an established SONET network.

Non-standard concatenation mapping for payloads

A switching apparatus is disclosed that employs a relatively simple and inexpensive switching matrix, but which avoids interruption of existing connections when connections are added or removed. The switching matrix switches errorlessly by controlling the point in time at which switching occurs. Using such a technique, switching can be performed without disturbing the connections already configured in the switching matrix, and so is referred to herein as being non-blocking. Optionally, the incoming data can be rearranged to provide a larger window of time in which the switching matrix can be switched. In the case of a switch using an optical backplane, this also allows more time for various components of the system (e.g., clock/data recovery units) to re-acquire lock. The switching apparatus includes a switching matrix and control circuitry. The switching matrix has a matrix input, a control input and a number of matrix outputs, and is configured to receive an information stream at the matrix input. The information stream includes a number of portions, while the control circuitry has a control output coupled to the control input. The control circuitry is configured to initially configure the switching matrix to output the information stream at a one of the matrix outputs and to subsequently configure the switching matrix to output the information stream at another of the matrix outputs during a period of time during which the one of the portions is transiting the switching matrix.

Method and apparatus for a rearrangeably non-blocking switching matrix

In a data transmission network, such as SONET, a method and apparatus for the generation of a path Alarm Insertion Signal (AIS) at the output of each of a number of concatenated pointer processors in response to a failure at the input of any one of the pointer processors. Each of the pointer processors has an input, an output and a bidirectional terminal that is coupled to a common node. Each of the pointer processors includes circuitry coupled to the input, the output and the bidirectional terminal that causes a predetermined logic level to be asserted at the bidirectional terminal in response to the appearance of an error signal at its input and that causes an AIS to appear at its output in response to either an error signal at its input or the assertion of the predetermined logic level at its bidirectional terminal.

Path AIS insertion for concatenated payloads across multiple processors

An apparatus and method for a synchronous optical network (SONET) includes ordering a plurality of signals of a first type in one or more line cards for transmit to one or more types of line cards, wherein the ordering of the first type of signals creates a plurality of independent signals of a second type, and transmitting the plurality of the first type of signals to the one or more types of line cards, wherein the independence of the signals of the second type permits the one or more types of signals of the second type to be in an arbitrary order. The method and apparatus includes ordering in a plurality of modules to assign to a variable A a number of basic modules on the one or more line cards, assign to a variable B a number of processors adapted for STS-N signals on the one or more line cards, calculate a variable C by dividing A by B, C being the number of basic module channels common to each of the processors, calculate a variable D by dividing C by three, D being a number of contiguous channels, divide each STS-N signal into N/D portions, each portion including up to D bytes, and for each portion of the STS-N signal, select one of the number of processors adapted for STS-N signals, and transmit the portion of the STS-N signal to the one of the number of processors.

Growing community of inventors

Allen, TX, United States of America

Lane Bryon Quibodeaux