Microsoft Technology Licensing, LLC

Intel Corporation

Other

Microsoft Corporation

Landy Wang

Yevgeniy Bak

Mehmet Iyigun

Arun Upadhyaya Kishan

Matthew Douglas Hendel

Ali-Reza Adl-Tabatabai

Gad Shlomo Sheaffer

Koichi Yamada

Jan Stephen Gray

Rene Antonio Vega

Martin Taillefer

David S Callahan

Ernest S Cohen

John Te-Jui Sheu

Sharvil A Nanavati

John R Douceur

Edmund Bernard Nightingale

Baskar Sridharan

Matthew Jeremiah Eason

Garrett Leischner

Andrew J Lagattuta

Cenk Ergan

Karan Mehra

Surendra Verma

William R Tipton

Kenneth Dean Johnson

David Hepkin

Alexander Kirshenbaum

Vadim Bassin

Kevin Michael Broas

Ervin Peretz

Malcolm James Smith

Brandon Allsop

Benjamin A Mickle

John D Vert

Joseph Cox Ballantyne

Yimin Deng

Matthew Ryan Miller

Richard M Shupak

Chiuchin Chen

Pavlo Lebedynskiy

Jordan Thomas Rabet

Vijay Sundaram

Tai Hing Tse

Yevgeniy (Eugene) Bak

Adam M Zabrocki

Shawn Daniel Hoffman

Arun U Kishan

David Alan Hepkin

Brandon Alec Allsop

Yevgeniy M Bak

Techniques for computer memory management are disclosed herein. In one embodiment, a method includes in response to receiving a request for allocation of memory, determining whether the request is for allocation from a first memory region or a second memory region of the physical memory. The first memory region has first memory subregions of a first size and the second memory region having second memory subregions of a second size larger than the first size of the first memory region. The method further includes in response to determining that the request for allocation of memory is for allocation from the first or second memory region, allocating a portion of the first or second multiple memory subregions of the first or second memory region, respectively, in response to the request.

Computer memory management in computing devices

Multiple partitions can be run on a computing device, each partition running multiple processes referred to as a workload. Each of the multiple partitions, is isolated from one another, preventing the processes in each partition from interfering with the operation of the processes in the other partitions. Using the techniques discussed herein, some memory pages of a partition (referred to as a sharing partition) can be shared with one or more other partitions. The pages that are shared are file backed (e.g., image or data files) or pagefile backed memory pages. The sharing partition can be, for example, a separate partition that is dedicated to sharing memory pages.

Shared memory in memory isolated partitions

Updating aging information for memory backing a virtual address-backed virtual machine (VM). A virtual memory address (VA) is allocated, within a page table entry (PTE), to a process backing the VM. Based on memory access(es) by the VM to a non-mapped guest-physical memory address (GPA), the GPA is identified as being associated with the VA; an HPA is allocated for the accessed GPA; a host-physical memory address (HPA) is associated with the VA within the PTE; the GPA is associated with the HPA within a second level address translation (SLAT) structure entry; and an accessed flag is set within the SLAT entry. Aging information is updated, including identifying the SLAT entry; querying a value of the accessed flag in the SLAT entry; clearing the accessed flag in the SLAT entry without invalidating the SLAT entry; and updating aging information for the VA and/or HPA based on the queried value.

Updating aging information using second-level address translation for virtual address-backed virtual machines

Aspects of the subject matter described herein relate to storage systems and aliased memory. In aspects, a file system driver or other component may send a request to a memory controller to create an alias between two blocks of memory. One of the blocks of memory may be used for main memory while the other of the blocks of memory may be used for a storage system. In response, the memory controller may create an alias between the blocks of memory. Until the alias is severed, when the memory controller receives a request for data from the block in main memory, the memory controller may respond with data from the memory block used for the storage system. The memory controller may also implement other actions as described herein.

Storage systems and aliased memory

Each program thread running on a computing device has an associated data stack and control stack. A stack displacement value is generated, which is the difference between the memory address of the base of the data stack and the memory address of the base of the control stack, and is stored in a register of a processor of the computing device that is restricted to operating system kernel use. For each thread on which return flow guard is enabled, prologue and epilogue code is added to each function of the thread (e.g., by a memory manager of the computing device). The data stack and the control stack each store a return address for the function, and when the function completes the epilogue code allows the function to return only if the return addresses on the data stack and the control stack match.

Return flow guard using control stack identified by processor register

A memory is made up of multiple pages, and different pages can have different priority levels. A set of memory pages having at least similar priority levels are identified and compressed into an additional set of memory pages having at least similar priority levels. The additional set of memory pages are classified as being the same type of page as the set of memory pages that was compressed (e.g., as memory pages that can be repurposed). Thus, a particular set of memory pages can be compressed into a different set of memory pages of the same type and corresponding to at least similar priority levels. However, due to the compression, the quantity of memory pages into which the set of memory pages is compressed is reduced, thus increasing the amount of data that can be stored in the memory.

Page-based compressed storage management

A set of memory pages from a working set of a program process, such as at least some of the memory pages that have been modified, are compressed into a compressed store prior to being written to a page file, after which the memory pages can be repurposed by a memory manager. The memory commit charge for the memory pages compressed into the compressed store is borrowed from the program process by a compressed storage manager, reducing the memory commit charge of the compressed storage manager. Subsequent requests from the memory manager for memory pages that have been compressed into a compressed store are satisfied by accessing the compressed store memory pages (including retrieving the compressed store memory pages from the page file if written to the page file), decompressing the requested memory pages, and returning the requested memory pages to the memory manager.

Reducing memory commit charge when compressing memory

A memory manager in a computer system that ages memory for high performance. The efficiency of operation of the computer system can be improved by dynamically setting an aging schedule based on a predicted time for trimming pages from a working set. An aging schedule that generates aging information that better discriminates among pages in a working set based on activity level enables selection of pages to trim that are less likely to be accessed following trimming. As a result of being able to identify and trim less active pages, inefficiencies arising from restoring trimmed pages to the working set are avoided.

Computer system with memory aging for high performance

In one embodiment, a memory management system temporarily maintains a memory page at an artificially high priority level. The memory management system may assign an initial priority level to a memory page in a page priority list. The memory management system may change the memory page to a target priority level in the page priority list after a protection period has expired.

Temporal standby list

A memory manager in a computing device allocates memory to programs running on the computing device, the amount of memory allocated to a program being a memory commit for the program. When a program is in a state where the program can be terminated, the content of the memory pages allocated to the program is compressed, and an amount of the memory commit for the program that can be released is determined. This amount of memory commit is the amount that was committed to the program less any amount still storing (in compressed format) information (e.g., data or instructions) for the program. The determined amount of memory commit is released, allowing that amount of memory to be consumed by other programs as appropriate.

Using memory compression to reduce memory commit charge

In one embodiment, the present invention includes a method for receiving control in a kernel mode via a ring transition from a user thread during execution of an unbounded transactional memory (UTM) transaction, updating a state of a transaction status register (TSR) associated with the user thread and storing the TSR with a context of the user thread, and later restoring the context during a transition from the kernel mode to the user thread. In this way, the UTM transaction may continue on resumption of the user thread. Other embodiments are described and claimed.

Handling operating system (OS) transitions in an unbounded transactional memory (UTM) mode

A system and method for mitigating memory errors in a computer system. Faulty memory is identified and tested by a memory manager of an operating system. The memory manager may perform diagnostic tests while the operating system is executing on the computer system. Regions of memory that are being used by software components of the computer system may also be tested. The memory manager maintains a stored information about faulty memory regions. Regions are added to the stored information when they are determined to be faulty by a diagnostic test tool. Memory regions are allocated to software components by the memory manager after checking the stored information about faulty memory regions. This ensures a faulty memory region is never allocated to a software component of the computer system.

Systematic mitigation of memory errors

Growing community of inventors

Honolulu, HI, United States of America

Landy Wang