Vlsi Technology, Inc.

Koninklijke Philips Corporation N.v.

Philips Semiconductor, Inc.

Nxp B.v.

Landon B Vines

Felix H Fujishiro

Chang-Ou Lee

Sigmund A Koenigseder

John L Cain

Ivan Sanchez

Danny W Echtle

Yu-Pin Han

Andrew J Black

Craig A Bellows

Liming Zhang

Hunter B Brugge

Albert H Liu

Walter D Parmantie

Annette Garcia

Parker A Wood

Jesse Guzman

Victor J Bass

Paul Douglas, Jr

Andrew Black

A slurry removal control mechanism for a CMP polisher is provided. After slurry dispense has been terminated, a high pressure fluid spray removes the slurry from the polishing pad, while the plated causes the pad to rotate at a high rpm rate, thus clearing the slurry from contact with the wafer. Additionally, there is provided a slurry dispense bar including high pressure spray nozzles for providing a high pressure spray upon slurry dispense termination.

CMP polisher substrate removal control mechanism and method

An anti-fuse structure and method for forming such structure. In one embodiment, the anti-fuse structure of the present invention includes a dielectric layer which is deposited over a metal layer. The semiconductor substrate is then masked and etched so as to form openings in the dielectric layer. Metal is deposited over the semiconductor substrate and is polished so as to remove the metal which overlies the dielectric layer so as to form a plug which extends through the dielectric layer and which electrically connects to the metal layer. An amorphous silicon block is then deposited, masked and etched so as to form an amorphous silicon block over the plug. A metal layer is then deposited, masked and etched so as to form an interconnect. The amorphous silicon block lies between the metal layer and the interconnect so as to prevent the flow of electrical current until such time as the anti-fuse is activated. The anti-fuse is activated by running a voltage higher than the threshold voltage of the anti-fuse between the interconnect and the plug. Upon activation of the anti-fuse, an electrical connection is made between the interconnect and the metal layer.

Method for forming strapless anti-fuse structure

In the manufacture of an integrated circuit, contaminated oxide is replaced by relatively pure oxide using the following steps. First, a partially manufactured integrated circuit is bathed in an aqueous solution of hydrogen peroxide and ammonium hydroxide to oxidize organic materials and weaken bonds of metal contaminants to the integrated circuit substrate. Second, an aqueous rinse removes the oxidized organic materials and metal contaminants. Third, the integrated circuit is bathed in an aqueous solution of hydrogen fluoride and nitric acid. The hydrogen fluroide etches the contaminated oxide; the nitric acid combines with calcium and metal contaminants freed as the oxide is etched. The resulting nitride byproducts are highly soluble and easily removed in the following aqueous rinse. A drying step removes rinse water from the integrated circuit. Finally, an oxide formation step provides a relatively pure oxide layer. In the case of a gate oxide, the method removes a sacrificial oxide in preparation for gate oxide growth. In the case of formation of the submetal dielectric, oxide formation involves an TEOS oxide deposition. A key advantage of the invention is the improved calcium removal due to the nitric acid.

Integrated circuit manufacture method with aqueous hydrogen fluoride and nitric acid oxide etch

The present invention is a fluid dispensing fixed abrasive polishing pad CMP system and method that utilizes fixed abrasive components to remove a portion or entire layer of a wafer while dispensing a fluid without suspended abrasive particles onto the wafer surface. A fluid dispensing fixed abrasive polishing pad is pressed against a wafer surface while rotating and fixed abrasive component apply a frictional force that planarizes a wafer surface. The fluid dispensed by the fluid dispensing fixed abrasive polishing pad assist the fixed components achieve wafer planarization in numerous ways, including minimizing scratching of the wafer surface, chemically reacting with the wafer surface to soften it, and aiding in the removal of particulate contaminants. The fluid flow in the present invention is strong enough to remove the waste (e.g., reaction products, wafer shavings, particulate contaminants, etc.) from the surface of the wafer and the fixed abrasive polishing pad during the polishing process. In one embodiment of the present invention, waste particles become suspended in the fluid and are sucked back through fluid dispensing ducts of the fluid dispensing fixed abrasive polishing pad.

Fluid dispensing fixed abrasive polishing pad

The present invention is directed to a method and apparatus for cleaning and enhancing CMP polishing pads. According to an example embodiment of the present invention, a fluid source supplies cleaning elements to a CMP pad conditioner arrangement at pressure of about 20 PSI. A dispensing arrangement is coupled to the fluid source and is adapted to disperse the cleaning elements and to dispense the elements onto a CMP pad. The high-pressure cleaning of the CMP pad improves the ability to clean the pad over existing methods, reduces processing defects, increases the pad life, and improves the uniformity of the polish rate.

CMP pad conditioner arrangement and method therefor

According to an example embodiment, the present invention comprises a CMP pad conditioner arrangement. An inlet is configured and arranged for receiving treatment elements. A distribution surface is coupled to the inlet and is configured and arranged to disperse the treatment elements. A multitude of outlets are coupled to the distribution surface and are configured and arranged to dispense the treatment elements onto a CMP pad. Benefits of using this embodiment include enhanced pad cleaning, better slurry dispense, improved wafer quality, and faster production.

The temperature of a wafer is controlled during a chemical mechanical polishing process. Fluid containment is provided on a wafer backing plate in contact with the wafer during the chemical mechanical polishing process. Transportation of fluid is provided to and from the fluid containment during the chemical mechanical polishing process. Temperature of the fluid is controlled in order to control temperature on the wafer during the chemical mechanical polishing process.

Temperature control carrier head for chemical mechanical polishing

An integrated circuit manufacturing method uses chemical-mechanical polishing (CMP) to planarize a nonplanar submetal (or intermetal) silica dielectric layer. The planarized device is cleaned with an aqueous solution of ammonium hydroxide and citric acid. Exposed hydrated silica is etched using mixture of nitric and hydrofluoric acids, freeing embedded contaminants from the CMP slurry. The hydrofluroic acid is the etching agent, while the nitric acid combines with the freed contaminants to render water soluble products. They are thus carried away in an aqueous rinse, whereas otherwise they might recontaminate the device. A metal interconnect structure is formed on the etched oxide by forming contact apertures, depositing metal, and patterning the metal. The method can be applied also to nonplanar intermetal dielectrics and subsequent metal interconnect layers. The result is an integrated manufacturing method with higher yields and a more reliable manufactured integrated circuit.

IC interconnect formation with chemical-mechanical polishing and silica

Metal to amorphous silicon to metal anti-fuse structure

Integrated-circuit manufacture method with aqueous hydrogen-fluoride and

The invention encompasses methods of forming pairs of transistor gates. In one aspect, the invention includes a method comprising: a) defining a first region and a second region of a substrate; the first region and second region comprising a first substrate surface and a second substrate surface, respectively; b) improving a lifetime of a low voltage tolerant transistor formed proximate the first substrate surface by cleaning the first substrate surface with a first mixture comprising hydrofluoric acid and hydrochloric acid; c) forming a first transistor gate over the first substrate region and incorporating the first transistor gate into the low-voltage tolerant transistor; and d) forming a second transistor gate over the second substrate region and incorporating the second transistor rate into a high-voltage tolerant transistor. In another aspect, the invention includes a method comprising: a) defining a first region and a second region of a substrate; the first region and second region comprising a first substrate surface and a second substrate surface, respectively; b) cleaning at least one of the first and second substrate surfaces with a first mixture comprising hydrofluoric acid and hydrochloric acid; c) after cleaning the at least one of the first and second substrate surfaces, forming a first oxide layer over the first and second substrate surfaces; d) removing the first oxide layer from over the first substrate surface while leaving the first oxide layer over the second substrate surface; and e) forming a second oxide layer over the first substrate surface.

Methods of forming pairs of transistors, and methods of forming pairs of

An antifuse structure and method for making the antifuse structure having a doped antifuse layer is disclosed. The doped antifuse layer is preferably deposited over a lower electrode. A barrier layer may then be formed over the doped antifuse layer and an upper electrode may subsequently be deposited over the barrier layer. The method of depositing the doped antifuse layer includes: (a) providing a chemical vapor deposition reactor having a support chuck for supporting a partially fabricated silicon wafer; (b) powering up the chemical vapor deposition reactor and heating the partially fabricated silicon wafer; (c) selecting a dopant species for the antifuse layer (e.g, n-type or p-type); (d) introducing a gaseous mixture of a silane compound and the selected dopant species into the chemical vapor deposition reactor with the aid of a neutral species; and (e) depositing the antifuse layer over the lower electrode. When the antifuse structure is programmed, a wider conduction path is formed in the doped antifuse layer and deprogrammed states are prevented.

Method for making doped antifuse structures

Titanium is deposited using a low-pressure chemical-vapor deposition to provide good step coverage over an underlying integrated circuit structure. A rapid thermal anneal is performed using an ambient including diborane. The rapid thermal anneal causes the titanium to interact with underlying silicon to form titanium silicide. Concurrently, the diborane reacts with the titanium to form titanium boride. A composite barrier layer results. Aluminum is deposited and then patterned together with the composite barrier layer to define a first level metalization. Subsequent intermetal dielectrics, metalization, and passivation layers can be added to form a multi-level metal interconnect structure. The titanium boride prevents the aluminum from migrating into the silicon, while the titanium silicide lowers the contact resistivity associated with the barrier layer. The relatively close match of the thermal coefficients of expansion for titanium boride and silicon provides high thermal stability.

Titanium boride and titanium silicide contact barrier formation for

A purge process for an LPCVD TEOS silicon dioxide deposition method uses a series of five purge cycles to allow low-defect wafer processing with less frequent chamber removal and cleaning. The purge process begins by loading dummy wafers into the chamber. Chamber pressure is reduced to below 20 mTorr. A maximal nonreactant gas flow for two minutes is used to dislodge and carry away contaminants such as flakes from silicon dioxide previously deposited on the chamber wall. After the first four of five purge cycles, the method returns to the reduction of chamber pressure, e.g., by maintaining the vacuum on while the gas sources are turned off. After the fifth cycle, the chamber is slowly filled with nitrogen until ambient pressure is reached. Then the dummy wafers are removed. The system is then ready for processing product wafers with reduced particle counts. The purge process is benign in that it only uses equipment and procedures of the type used during product wafer processing. Maintenance involving chamber removal and cleaning is required much less often so that manufacturing throughput is enhanced.

Semiconductor wafer manufacturing process with high-flow-rate

An improved anneal process is disclosed for use in the preparation of a dielectric layer, especially an intermetal dielectric layer. An oxide layer is deposited using a H.sub.2 O-TEOS PECVD process. A vacuum bake is used to minimize or eliminate volatile water, hydrogen, and hydrocarbon impurities in the dielectric layer. An oxidation anneal is then performed to scavenge any remaining undesirable species, and to provide for densification of the dielectric layer.

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San Antonio, TX, United States of America

Landon B Vines