Micron Technology Incorporated

Lance Williamson

Adam L Olson

Kaveri Jain

William R Brown

Robert Dembi

Durai Vishak Nirmal Ramaswamy

Matthew J King

Ashonita A Chavan

Beth R Cook

Chandra S Tiwari

Yi Hu

Daniel Billingsley

Yiping Wang

Wei Yeeng Ng

Andrew Li

Xiaosong Zhang

Sameer Chhajed

Michael Mutch

Ramey M Abdelrahaman

Kamal Kumar Muthukrishnan

Narula Bilik

Zhenyu Bo

Joan M Kash

David Neumeyer

Yung K Pak

A memory cell comprises a capacitor comprising a first capacitor electrode having laterally-spaced walls, a second capacitor electrode comprising a portion above the first capacitor electrode, and capacitor insulator material between the second capacitor electrode and the first capacitor electrode. The capacitor comprises an intrinsic current leakage path from one of the first and second capacitor electrodes to the other through the capacitor insulator material. A parallel current leakage path is between the second capacitor electrode and the first capacitor electrode. The parallel current leakage path is circuit-parallel with the intrinsic current leakage path, of lower total resistance than the intrinsic current leakage path, and comprises leaker material that is everywhere laterally-outward of laterally-innermost surfaces of the laterally-spaced walls of the first capacitor electrode. Other embodiments, including methods, are disclosed.

Memory cells and methods of forming a capacitor including current leakage paths having different total resistances

A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material comprises longitudinally-alternating first and second regions that individually have a vertically-elongated seam therein. The vertically-elongated seam in the first regions are taller than in the second regions. Additional embodiments, including method, are disclosed.

Memory arrays and methods used in forming a memory array comprising strings of memory cells

Methods of forming staircase structures. The method comprises forming a patterned hardmask over tiers. An exposed portion of an uppermost tier is removed to form an uppermost stair. A first liner material is formed over the patterned hardmask and the uppermost tier, and a portion of the first liner material is removed to form a first liner and expose an underlying tier. An exposed portion of the underlying tier is removed to form an underlying stair in the underlying tier. A second liner material is formed over the patterned hardmask, the first liner, and the second liner. A portion of the second liner material is removed to form a second liner and expose another underlying tier. An exposed portion of the another underlying tier is removed to form another underlying stair. The patterned hardmask is removed. Staircase structures and semiconductor device structure are also disclosed.

Apparatus comprising staircase structures

Methods of forming staircase structures

Growing community of inventors

Boise, ID, United States of America

Lance Williamson