Texas Instruments Corporation

Lance Stanford Robertson

Jiong-Ping Lu

Donald S Miles

James David Bernstein

Said Ghneim

Henry Litzmann Edwards

Tathagata Chatterjee

Jeffrey Loewecke

Jiejie Xu

Binghua Hu

Duofeng Yue

Martin B Mollat

Richard B Irwin

Amitava Chatterjee

Lindsey H Hall

Kaiping Liu

Shyh-Horng Yang

Hisashi Shichijo

Srinivasan Chakravarthi

Song Zhao

Sue E Crank

Brian Edward Hornung

Juanita DeLoach

Xin Zhang

Xiaozhan Liu

Benjamin Moser

Nandu Mahalingam

Beriannan Chidambaram

The present invention provides a method for implanting charged particles in a substrate and a method for manufacturing an integrated circuit. The method for implanting charged particles in a substrate, among other steps, includes projecting a beam of charged particles () to a substrate (), the beam of charged particles () having a given beam divergence; and forming a diverged beam of charged particles () by subjecting the beam of charged particles () to an energy field (), thereby causing the beam of charged particles () to have a larger beam divergence. The method then desires implanting the diverged beam of charged particles () into the substrate ().

Divergent charged particle implantation for improved transistor symmetry

One embodiment of the invention relates to an integrated circuit. The integrated circuit includes a first matched transistor comprising: a first source region, a first drain region formed within a first drain well extension, and a first gate electrode having lateral edges about which the first source region and first drain region are laterally disposed. The integrated circuit also includes a second matched transistor comprising: a second source region, a second drain region formed within a second drain well extension, and a second gate electrode having lateral edges about which the second source region and second drain region are laterally disposed. Analog circuitry is associated with the first and second matched transistors, which analog circuitry utilizes a matching characteristic of the first and second matched transistors to facilitate analog functionality. Other devices, methods, and systems are also disclosed.

Matched analog CMOS transistors with extension wells

The present invention provides a method for manufacturing a semiconductor device. In one embodiment, the method for manufacturing the semiconductor device includes a method for manufacturing a zener diode, including among others, forming a doped well () within a substrate () and forming a suppression implant () within the substrate (). The method for manufacturing the zener diode may further include forming a cathode () and an anode () within the substrate (), wherein the suppression implant () is located proximate the doped well () and configured to reduce threading dislocations.

Method for reducing dislocation threading using a suppression implant

The present invention provides a method for manufacturing a semiconductor device. In one embodiment, the method for manufacturing the semiconductor device includes a method for manufacturing a zener diode, including among others, forming a doped well within a substrate and forming a suppression implant within the substrate. The method for manufacturing the zener diode may further include forming a cathode and an anode within the substrate, wherein the suppression implant is located proximate the doped well and configured to reduce threading dislocations.

The present invention provides a method for manufacturing a semiconductor device. In one embodiment of the present invention, without limitation, the method for manufacturing the semiconductor device includes forming a gate structure () over a substrate () and forming source/drain regions () in the substrate () proximate the gate structure (). The method further includes forming fluorine containing regions () in the source/drain regions () employing a fluorine containing plasma using a power level of less than about 75 Watts, forming a metal layer () over the substrate () and fluorine containing regions (), and reacting the metal layer () with the fluorine containing regions () to form metal silicide regions () in the source/drain regions ().

Method for manufacturing a semiconductor device containing metal silicide regions

The present invention provides a method for implanting charged particles in a substrate and a method for manufacturing an integrated circuit. The method for implanting charged particles in a substrate, among other steps, includes projecting a beam of charged particles () to a substrate (), the beam of charged particles () having a given beam divergence, and forming a diverged beam of charged particles () by subjecting the beam of charged particles () to an energy field (), thereby causing the beam of charged particles () to have a larger beam divergence. The method then desires implanting the diverged beam of charged particles () into the substrate ().

A silicideis formed in exposed silicon on a semiconductor waferby a method that includes forming a thin interface layerover the semiconductor waferand performing a first low temperature anneal to create the silicideThe method further includes removing an unreacted portion of the interface layerand performing a second low temperature anneal to complete the formation of a low resistance silicide

Silicide formation using a low temperature anneal process

The present invention provides a method for implanting ions in a substrate and a method for manufacturing an integrated circuit. The method for implanting ions in a substrate, among other steps, including placing a substrate () on an implant platen () such that a predominant axes () of the substrate () is rotated about 30 degrees to about 60 degrees or about 120 degrees to about 150 degrees offset from a radial with respect to the implant platen (), and further wherein the substrate () is not tilted. The method further includes implanting ions into the substrate (), the rotated position of the predominant axes () reducing shadowing.

Implant optimization scheme

The present invention provides a method for implanting a dopant in a substrate and a method for manufacturing a semiconductor device. The method for implanting a dopant, among other steps, including tilting a substrate () located on or over an implant platen () about an axis in a first direction with respect to an implant source () and implanting a portion of an implant dose within the substrate () tilted in the first direction. The method further includes tilting the substrate () having already been tilted in the first direction about the axis in a second opposite direction, and implanting at least a portion of the implant dose within the substrate () tilted in the second opposite direction.

Method for implanting dopants within a substrate by tilting the substrate relative to the implant source

Fluorine containing regions () are formed in the source and drain regions () of the MOS transistor. A metal layer () is formed over the fluorine containing regions () and the source and drain regions (). The metal layer is reacted with the underlying fluorine containing regions to form a metal silicide.

Integrated circuit metal silicide method

The present invention provides, in one embodiment, a method of fabricating a semiconductor device (). The method comprises growing an oxide layer () on a gate structure () and a substrate () and implanting a dopant () into the substrate () and the oxide layer (). Implantation is such that a portion of the dopant () remains in the oxide layer () to form an implanted oxide layer (). The method further includes depositing a protective oxide layer () on the implanted oxide layer () and forming etch-resistant off-set spacers (). The etch-resistant off-set spacers () are formed adjacent sidewalls of the gate structure () and on the protective oxide layer (). The etch resistant off-set spacers having an inner perimeter () adjacent the sidewalls and an opposing outer perimeter (). The method also comprises removing portions of the protective oxide layer () lying outside the outer perimeter () of the etch-resistant off-set spacers (). Other embodiments of the present invention include a transistor device () and method of manufacturing an integrated circuit ().

Semiconductor device having optimized shallow junction geometries and method for fabrication thereof

A method for forming metal silicide regions in source and drain regions () is described. Prior to the thermal annealing of the source and drain regions (), germanium is implanted into a semiconductor substrate adjacent to sidewall structures () formed adjacent gate structures (). The position of the implanted germanium species in the semiconductor substrate will overlap the source and drain regions (). Following thermal annealing of the source and drain regions (), the implanted germanium prevents the formation of metal silicide spikes.

Silicide method for CMOS integrated circuits

A method of forming a semiconductor device includes forming at least one amorphous region within an at least partially formed semiconductor device. The method also includes implanting a halogen species in the amorphous region of the at least partially formed semiconductor device. The method further includes doping at least a portion of the at least one amorphous region to form at least one junction within the at least partially formed semiconductor device. The method also includes performing solid phase epitaxial re-growth to activate the doped portion of the at least one amorphous region of the at least partially formed semiconductor device.

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Rockwall, TX, United States of America

Lance Stanford Robertson