International Business Machines Corporation

Lance M Venarchick

Richard Gerard Hofmann

Patrick M Bland

Dennis L Moeller

Daniel R Cronin, Iii

Moises Cases

Stephen Douglas Weitzel

Suksoon Yong

Sagi Katz

A bridge for interfacing buses in a computer system having an industry standard architecture (ISA) bus and a peripheral controller interconnect (PCI) bus is coupled between the ISA and PCI buses. The bridge has a direct memory access (DMA) control circuit programmable by programming signals to perform a DMA transfer. The DMA has registers for storing base addresses and registers for storing current addresses. The base addresses and the current addresses indicate destinations of transfer data in the DMA transfer. A power management device is coupled to the DMA control circuit and has logic for causing the computer system to enter a suspend mode. A base address register read circuit is coupled to the base address registers. Prior to entering the suspend mode, the base address register read circuit provides one of the base addresses to be read by a central processing unit (CPU) onto disk storage. When the power management device resumes operation of the computer system, the base address that has been read is written back to reprogram the DMA control circuit. The ability to read the base address registers and store base addresses allows a reduction or elimination of shadow registers that shadow every write to a base address register.

Bridge between two buses of a computer system with a direct memory

A system having an industry standard architecture (ISA) bus with a 24-bit memory addressing capacity and a peripheral controller interconnect (PCI) bus with a 32-bit memory addressing capacity, is provided with a bridge coupled between the ISA and PCI buses. The bridge has a direct memory access (DMA) controller circuit that generates 32-bit memory addresses for DMA transfer operations over the PCI bus. The DMA controller circuit includes a pair of cascaded DMA controllers that generate the 16 least significant bits of the 32-bit memory addresses, and address extension logic having a low page register that provides the 8 next most significant bits of the 32-bit memory addresses, and a high page register that provides the 8 most significant bits of the 32-bit memory addresses. The 16 bits provided by the low and high page registers are concatenated with the lower 16 bits to form the 32-bit addresses. The DMA controller circuit is also provided with count extension logic that increases the transfer count from a 16-bit number to a 24-bit number, so that larger segments of memory may be moved in the individual DMA transfers.

A computer system having a peripheral controller interconnect (PCI) bus and an industry standard architecture (ISA), with ISA compatible devices coupled to the ISA bus, is provided with a first bridge coupled between the PCI and ISA buses. The first bridge has a first direct memory access (DMA) control circuit for controlling DMA transfers with the ISA devices. In order to achieve expanded compatibility with other types of devices, the system is also provided with an expansion bus, such as a Microchannel bus, with Microchannel compatible devices coupled to the Microchannel bus. A second bridge is coupled between the PCI and the Microchannel buses. This second bridge has a second DMA control circuit that controls DMA transfers with the ISA devices and with the Microchannel devices. Software disables the first DMA control circuit such that only the second DMA control circuit controls DMA transfers within the computer system.

Computer system having a bridge between two buses with a direct memory

A bridge interface for buses in a computer system has a direct memory access (DMA) controller that controls memory transfers in the computer system. The DMA controller has a pair of cascaded DMA controller chips that provide a plurality of DMA channels. A multiplexer circuit receives memory address signals from the DMA controller chips. The memory address signals are received in both a shifted form and an unshifted form at the multiplexer inputs. By selection of the shifted or the unshifted memory address at the multiplexer, either even or odd addresses are produced at the multiplexer output for each DMA channel, thereby selectively providing 8-bit or 16-bit memory accesses. The control of the multiplexer is programmable for each DMA channel, providing dynamic configuration of the DHA channels as either 8-bit or 16-bit channels.

Bridge for interfacing buses in computer system with a direct memory

A bridge is provided between an industry standard architecture (ISA) bus and a peripheral controller interconnect (PCI) bus and performs memory cycles on both buses simultaneously when a master on the ISA bus initiates a memory transfer. Data is steered between the ISA and PCI buses when a slave on the PCI bus claims the memory address within a predetermined time period after the memory cycle is initiated on the PCI bus. The ISA bus is isolated from the PCI bus when no slave on the PCI bus claims the memory address. This allows the memory cycle to be completed on the ISA bus, and the memory cycle on the PCI bus is terminated.

Bridge between two buses of a computer system that determines the

A bridge interface for a computer system having an industry standard architecture (ISA) bus and a peripheral controller interconnect (PCI) bus is coupled between the ISA and PCI buses. The bridge has a direct memory access (DMA) control circuit programmable by programming signals to perform a DMA transfer, and a scatter/gather unit coupled between the ISA bus and the DMA control circuit. The scatter/gather unit selectively provides the programming signals to the DMA control circuit directly or causes the programming signals to be provided over the ISA bus. Providing the programming signals to the DMA control circuit directly from the programming controller of the scatter/gather unit takes advantage of the location of both the DMA control circuit and the scatter/gather unit on the bridge chip. The program controller is able to program the DMA control circuit with I/O write cycles that take only one 33 MHz clock, instead of a plurality of 8 MHz clocks if the DMA control circuit is programmed with signals sent over the ISA bus. This provides an order of magnitude reduction is the time required to program the DMA control circuit.

Bridge interface between two buses of a computer system with a direct

A bridge for interfacing buses in a computer system having an industry standard architecture (ISA) bus and a peripheral controller interconnect (PCI) bus is coupled between the ISA and PCI buses. Devices coupled to the buses are either PCI bus-compliant devices or are non-PCI bus-compliant devices. A power management device in the computer system is able to place the computer system into a low power suspend mode, a resume mode and an active mode. The bridge has a multi-tiered arbitration device for arbitrating among the PCI bus-compliant devices and the non-PCI bus-compliant devices for control of the computer system. The arbitration device is responsive to the power management device to controllably suspend arbitration when the power management device indicates that the suspend mode is being entered.

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Boca Raton, FL, United States of America

Lance M Venarchick