Stmicroelectronics Gmbh

United Technologies Corporation

Adaptec, Inc.

Optics Research, Inc.

Lance Leslie Flake

Timothy Richard Feldman

Michael W Yeager

Roger G Cox

Gregory Black Shonle

A cache system and a method for an extent-based cache memory design are disclosed. The method Includes providing a storage device and a host device where each device is in communication with the memory and creating an extent record associated with the memory. A storage device access request is received from the host device and at least one state field value in the extent record is changed in response to the access request from the host device. The size of an extent associated with the extent record and allocated within the memory may be based on the access request and any additional speculative data. The at least one state field value may be selected from the group consisting of extent size, valid count, hit count, and dirty count. The storage device may be implemented as an intelligent hard disk drive and the memory may be implemented by random access memory (RAM).

Extended cache memory system and method for caching data including changing a state field value in an extent record

A digital data separator that is capable of separating data signals and clock signals from an encoded data stream. The digital data separator includes a synchronizer to synchronize the encoded data stream with the system clock of the digital data separator. An up-counter counts the number of clock pulses between valid logic 1's in the encoded digital data stream. Combination logic compares the value of the up-counter with established threshold values to determine whether the data separator has received a valid logic 1. The combinatorial logic also reset the up-counter on determining that a valid logic 1 was received.

Digital data separator

A cache system and method for configuring and accessing a cache that enables a binary-sized memory space to be efficiently shared amongst cache and non-cache uses. A storage device is provided having a plurality of blocks where each block is identified with a block address. An access request identifies a target block address. The target block address includes an upper portion and a lower portion. A non-binary divide is performed on the upper portion to produce a quotient and a remainder. The remainder portion is combined with the lower portion to create an index. The index is applied to a tag memory structure to select an entry or set of entries in the tag memory structure. The content of the selected entry is compared to the quotient portion to determine if the target block is represented in the cache.

Division of memory into non-binary sized cache and non-cache areas

A gated scan flop circuit and methods of making the gated scan flop circuit are provided. In one example, the scan flop circuit includes a sub-scan flop circuit that incorporates a multiplexer and a flip flop circuit, and a data terminal D that is connected to the sub-scan flop circuit. Also provided is a first logic gate that is configured to receive a scan input terminal SI and a clock gate terminal G. The first logic gate has a first logic gate output that is connected to the sub-scan flop circuit. A scan enable terminal SE is connected to the sub-scan flip circuit, and a latch circuit is configured to receive the clock gate terminal G, and track its input while the clock terminal CLK is inactive. A second logic gate having a second logic gate output is provided that is configured to receive as inputs the scan enable terminal SE and the latched clock gate terminal G. A third logic gate is configured to receive a clock terminal CLK and the second logic gate output. The third logic gate has a third logic gate output that is connected to the sub-scan flop circuit. The gated scan flop circuit has an output Q and a complementary output /Q. In this example, the first logic gate, the latch circuit, the second logic gate, the third logic gate, and the sub-scan flop circuit are internally integrated circuit components of the scan flop circuit.

Gated clock flip-flops

A method comprises receiving a diskette into a drive, determining the logical format type of the data written on the diskette, and targeting any recorded track on either surface of the diskette that has both inner and outer adjacent tracks. The head actuator in the drive is moved to the expected position for the targeted track that has been determined by a factory precalibration. The head actuator is then stepped inside by one sixteenth of the width of a standard track pitch and an attempt is made to read a sector header from the recorded track. If the reading of the sector header succeeded, the head actuator is stepped in again by one sixteenth and the sector header is read again. Such inward stepping is continued until the reading of the sector header fails. The radial position at which this occurs is defined as the inner boundary of the track. The outer boundary is found in similar fashion. The track center is computed as the midpoint between such inner and outer boundaries. The track centers for all the other tracks on the diskette are then assumed to be consistently registered from the targeted track's center.

Method of compensating for the misregistration of the radial track

A pipelined arithmetic processor includes a pair of multipliers in parallel feeding an ALU that, in turn, feeds a pair of parallel accumulators, the various sections being connected by controllable data paths and controlled by a set of pipelined registers feeding a series of decoders.

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Boulder, CO, United States of America

Lance Leslie Flake