Pericom Semiconductor Corporation

Xaqti, Corporation

Lance K Lee

Ramon S Co

Jyn-Bang Shyu

David Y Wang

Disclosed is a data/clock recovery system for use in a high speed networking transceiver units. The data/clock recovery system includes a four phase sampler circuit that is configured to receive a data input waveform and produce output data. A transition detect circuit that is arranged to receive the output data produced by the four phase sampler circuit. The transition detect circuit is configured to determine whether a clock is leading or lagging the data input waveform. A counter for shifting the clock if the clock is determined by the transition detect circuit to either be leading or lagging the data input waveform, such that the shifting is configured to synchronize the clock and the data input waveform. A decoder that receives control signals from the counter, such that the decoder generates a selection signal. The data/clock recovery system further including a multiplexer for selecting four predetermined clock phases in response to the selection signal generated by the decoder. Preferably, the four predetermined clock phases are continually shifted by the counter if the clock and the data input waveform are not synchronized.

Multi-phase data/clock recovery circuitry and methods for implementing same

A jitter attenuator receives data and a receive clock extracted from an input data stream. A transmit clock is generated for retransmitting the data. The transmit clock has less jitter than the receive clock but has the same average frequency. An elastic buffer or FIFO is necessary to buffer the data. The receive clock is divided into a series of write clocks for writing data into the elastic buffer, and the transmit clock is also divided into a series of read clocks for reading data from the elastic buffer. A series of multi-phase clocks is used to generate the transmit clock. The multi-phase clocks all have the same frequency but are offset in phase from one another. A phase selector, under control of a counter, selects one of the multi-phase clocks to be the transmit clock. The counter is incremented or decremented by a phase comparator. The phase comparator compares the phase of one of the write clocks to the phase of one of the read clocks. The counter is incremented when the phase of the write clock lags the read clock, selecting a multi-phase clock with a more retarded phase, but the counter is decremented when the write clock leads the read clock, selecting a multi-phase clock with a more advanced phase. Thus the phase of the transmit clock is adjusted by the phase comparison of the write and read clocks for the elastic buffer. The elastic buffer is forced to half-full by comparing a write and read clock that are separated by half the capacity of the buffer. The phase, rather than the frequency, is adjusted, eliminating the feedback to an external VCO, allowing the jitter attenuator to be integrated on a single silicon substrate.

Growing community of inventors

Milpitas, CA, United States of America

Lance K Lee