International Business Machines Corporation

Trident Microsystems (far East) Ltd.

Lance G Hehenberger

John Andrew Schumann

Debapriya Chatterjee

Paul Frank Lecocq

Karen E Yokum

Bryant Cockcroft

Paul Umbarger

Tharunachalam Pindicura

Jeffrey W Kellington

Kevin Barnett

Jamory Hawkins

Lawrence Leitner

Omesh Bajaj

Alan G Gara

Martin Ohmacht

Thomas M Gooding

Mark Edwin Giampapa

David A Campbell

George W Rohrbaugh, Iii

Rudolf Adriaan Haring

Matthew Roger Ellavsky

John Martin Ludden

Madhusudan Kadiyala

Matthew Damian Bates

Ralph E Bellofatto

A method of checking for a stall condition in a processor is disclosed, the method including inserting an inline instruction sequence into a thread, the inline instruction sequence configured to read the result from a timing register during processing of a first instruction and store the result in a first general purpose register, wherein the timing register functions as a timer for the processor; and read the results from the timing register during processing of a second instruction and store the results in a second general purpose register, wherein the second instruction is the next consecutive instruction after the first instruction. The inline thread sequence may be inserted in sequence with the thread and further configured to compare the difference between the result in the first and second general purpose register to a programmable threshold.

Method and system for detection of thread stall

Verification of asynchronous page fault in a simulated environment. The methods include providing a simulated environment that includes a simulated processor core, a memory, and an interrupt handler. The methods also include executing a test code in the simulated environment by: executing a non-irritator thread code comprising a plurality of load instructions that span at least two slices of the simulated processor core, executing a first irritator thread code to bias against the execution of the plurality of load instruction by one of the at least two slices of the simulated processor core, and executing a second irritator thread code to invalidate caching of page table entries during execution of the plurality of load instructions in a fast access cache memory.

Methods and systems for verifying out-of-order page fault detection

An apparatus and method for evaluating a state of an electronic or integrated circuit (IC), each IC including one or more processor elements for controlling operations of IC sub-units, and each the IC supporting multiple frequency clock domains. The method comprises: generating a synchronized set of enable signals in correspondence with one or more IC sub-units for starting operation of one or more IC sub-units according to a determined timing configuration; counting, in response to one signal of the synchronized set of enable signals, a number of main processor IC clock cycles; and, upon attaining a desired clock cycle number, generating a stop signal for each unique frequency clock domain to synchronously stop a functional clock for each respective frequency clock domain; and, upon synchronously stopping all on-chip functional clocks on all frequency clock domains in a deterministic fashion, scanning out data values at a desired IC chip state. The apparatus and methodology enables construction of a cycle-by-cycle view of any part of the state of a running IC chip, using a combination of on-chip circuitry and software.

Method and apparatus to debug an integrated circuit chip via synchronous clock stop and scan

A system for encrypting and decrypting data is provided. The system includes a client for receiving a data packet, setting a value of a crypto bit, and transmitting the data packet over a system bus. A crypto module receives the data packet from the system bus and performs a cryptology function on the data packet based on a first value of the crypto bit. A memory controller receives the data packet from the system bus and performs non-cryptology functions on the data packet based on a second value of the crypto bit.

Encoded digital video content protection between transport demultiplexer and decoder

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Leander, TX, United States of America

Lance G Hehenberger