Intel Corporation

Other

Lance E Hacking

Ramana V Rachakonda

Shreekant S Thakkar

Belliappa Manavattira Kuttanna

Rajesh Bhikhubhai Patel

Shivnandan D Kaushik

Jeffrey R Wilcox

Cormac Brick

Debbie Marr

David I Poisner

Stephen H Gunther

Jasmin Ajanovic

Chee Hak Teh

Gautham N Chinya

Devadatta V Bodas

Bryant E Bigbee

Sridhar Muthrasanallur

Shahrokh Shahidzadeh

Vladimir M Pentkovski

Kenneth C Creta

Ashish V Choubal

Aaron T Spink

Sankaran M Menon

Thomas R Huff

Om Ji Omer

Huichu Liu

Arnab Raha

Siva Ramakrishnan

Debabrata Mohapatra

Mahesh K Reddy

Binta M Patel

Bernard Lint

John P Lee

Lori R Borger

Pawitter P Bhatia

Subramaniam M Maiyuran

Alon Naveh

Blaise B Fanning

Sreenivas Subramoney

Srinivas Chennupaty

Roger A Golliver

Patrice L Roussel

Karunakara Kotary

Kenneth D Shoemaker

Kushagra V Vaid

Salvador Palanca

Sanjoy K Mondal

Larry Edward Thatcher

Dipan Kumar Mandal

Bruce L Fleming

Hsien-Cheng Emile Hsieh

Terry M Fletcher

Todd Aldridge Dutton

Anil K Sabbavarapu

Hee-Jun Park

Eric L Hendrickson

Biji George

Avishaii Abuhatzera

Steven Scott Varnum

Victor Ruybalid

Ping Sager

Sabar Mourad Souag

Jeremy Conner

Noel Eck

William Hodges

Michael E Altenburg

David K Dean

Ritwika Chowdhury

Methods and systems include a neural network system that includes a neural network accelerator. The neural network accelerator includes multiple processing engines coupled together to perform arithmetic operations in support of an inference performed using the deep neural network system. The neural network accelerator also includes a schedule-aware tensor data distribution circuitry or software that is configured to load tensor data into the multiple processing engines in a load phase, extract output data from the multiple processing engines in an extraction phase, reorganize the extracted output data, and store the reorganized extracted output data to memory.

Schedule-aware tensor distribution module

An apparatus to facilitate accelerating neural networks with low precision-based multiplication and exploiting sparsity in higher order bits is disclosed. The apparatus includes a processor comprising a re-encoder to re-encode a first input number of signed input numbers represented in a first precision format as part of a machine learning model, the first input number re-encoded into two signed input numbers of a second precision format, wherein the first precision format is a higher precision format than the second precision format. The processor further includes a multiply-add circuit to perform operations in the first precision format using the two signed input numbers of the second precision format; and a sparsity hardware circuit to reduce computing on zero values at the multiply-add circuit, wherein the processor to execute the machine learning model using the re-encoder, the multiply-add circuit, and the sparsity hardware circuit.

Accelerating neural networks with low precision-based multiplication and exploiting sparsity in higher order bits

A disclosed apparatus to multiply matrices includes a compute engine. The compute engine includes multipliers in a two dimensional array that has a plurality of array locations defined by columns and rows. The apparatus also includes a plurality of adders in columns. A broadcast interconnect between a cache and the multipliers broadcasts a first set of operand data elements to multipliers in the rows of the array. A unicast interconnect unicasts a second set of operands between a data buffer and the multipliers. The multipliers multiply the operands to generate a plurality of outputs, and the adders add the outputs generated by the multipliers.

Methods, apparatus, articles of manufacture to perform accelerated matrix multiplication

A method and apparatus for dynamic power management of memories. In one embodiment of the invention, the power consumption of the memories is reduced based on the operating state of the memories. For example, in one embodiment of the invention, the power supply to the memories is reduced when the memories are in an inactive state by reducing and/or turning off the input voltage(s) to the memories. In one embodiment of the invention, the processing unit dynamically changes the strength of the On-Die Termination pull-up/pull-down resistance based on the memory operating mode, memory voltage, and memory temperature.

Method and system for dynamic power management of memories

Techniques of debugging a computing system are described herein. The techniques may include generating debug data at agents in the computing system. The techniques may include recording the debug data at a storage element, wherein the storage element is disposed in a non-core portion of the circuit interconnect accessible to the agents.

Debug interface

In one embodiment, the present invention includes a system-on-a-chip (SoC) with first and second cores, interface logic coupled to the cores, chipset logic coupled to the interface logic, and a virtual firewall logic coupled between the chipset logic and the second core. The interface logic may include a firewall logic, a bus logic, and a test logic, and the chipset logic may include a memory controller to provide for communication with a memory coupled to the SoC. In some system implementations, both during test operations and functional operations, the second core can be disabled during normal operation to provide for a single core SoC, enabling greater flexibility of use of the SoC in many different implementations. Other embodiments are described and claimed.

Interface logic for a multi-core system-on-a-chip (SoC)

A technique to monitor events within a computer system or integrated circuit. In one embodiment, a software-accessible event monitoring storage and hardware-specific monitoring logic are selectable and their corresponding outputs may be monitored by accessing a counter to count events corresponding to each of software-accessible storage and hardware-specific monitoring logic.

Technique for monitoring activity within an integrated circuit

Systems and methods of processing write transactions provide for combining write transactions on an input/output (I/O) hub according to a protocol between the I/O hub and a processor. Data associated with the write transactions can be flushed to an I/O device without the need for proprietary software and specialized registers within the I/O device.

Write combining protocol between processors and chipsets

A method to reduce idle leakage power in I/O pins of an integrated circuit using external circuitry. Initially, I/O pins on a package are subdivided into those that will also remain powered up and those that will power down during idle state. When a system enters a low power mode, a signal is sent to the external circuitry. The signal notifies the I/O pins that always remain powered up to notify the external circuitry to power down the other set of I/O pins.

Reducing idle leakage power in an IC

A technique to promote determinism among multiple clocking domains within a computer system or integrated circuit, In one embodiment, one or more execution units are placed in a deterministic state with respect to multiple clocks within a processor system having a number of different clocking domains.

Technique for promoting determinism among multiple clock domains

An interconnect bandwidth throttler is disclosed. The interconnect bandwidth throttler turns off the interconnect, based on whether a maximum number of transactions has taken place within a predetermined throttle window. Both the maximum number of transactions and the throttle window are adjustable. Characteristics such as performance, thermal considerations, and average power are adjustable using the interconnect bandwidth throttler.

Interconnect bandwidth throttler

An interconnect bandwidth throttler is disclosed. The interconnect bandwidth throttler turns off the interconnect, based on whether a maximum number of transactions has take place within a predetermined throttle window. Both the maximum number of transactions and the throttle window are adjustable.

Growing community of inventors

Austin, TX, United States of America

Lance E Hacking