Sun Microsystems, Inc.

Advanced Silicon Display Optoelectronics Corporation Ltd.

Netlogic Microsystems, Inc

Lan Lee

Cong K Khieu

Yi Li

Kevin B Normoyle

Cong Quoc Khieu

Michael E Ichiriu

Massimo Sutera

Der-Ren Chu

Sung-Hun Oh

Xin Liu

Masaru Shinohara

Rong Hsu

Yuefei Ge

Hiep P Ngo

David A Bunsey, Jr

Daniel Y Cheung

Shi-Chin Ou-Yang

Ivana Capellano

The present disclosure discloses a display driving method, a display driver chip and a liquid crystal display device. The display driving method includes: within a display duration of a first bit-plane data, controlling the display device to display the first bit-plane data; when a loading duration of a single bit-plane data is longer than the display duration of the first bit-plane data, after completing the display of the first bit-plane data, controlling a pixel liquid crystal layer corresponding to the first bit-plane data in the display device to return to a target state, and completing loading of a second bit-plane data while maintaining the pixel liquid crystal layer corresponding to the first bit-plane data in the target state. Based on the above method, the cost of data driving can be effectively reduced, and the display effect of the liquid crystal display device can be improved.

Display driving method, display driver chip and liquid crystal display device

A display control circuit applies to a LCoS panel including pixel units and a substrate. The display control circuit includes a pixel memory array circuit and a driving circuit. The pixel memory array circuit includes pixel memory units. A projection of the pixel memory array circuit on the substrate is in a projection of the pixel units on the substrate. The driving circuit includes a row driving circuit and a column driving circuit. A projection of the driving circuit on the substrate is outside the projection of the pixel units on the substrate. The driving circuit provides a modulation signal and pixel data. The pixel memory array circuit modulates the pixel data by the modulation signal to provide a pixel display voltage to each of the pixel units.

Display control circuit and liquid crystal on silicon panel

In an embodiment, present application describes a system and method to detect the alignment of multiple clocks in multi-clock domains system. In some variations, multiple clocks are derived from one or more reference clocks using various PLLs. The derived clocks maintain frequency relationship with the reference clock. In some variations, a relationship between the frequencies of various clocks is used to generate the alignment signals in the domain of one of the clocks.

Method and circuitry for phase align detection in multi-clock domain

A content addressable memory (CAM) has a main array including a plurality of rows of CAM cells, one or more spare rows of CAM cells selectable to functionally replace defective rows of CAM cells in the main array, and a control circuit for disabling the defective rows by writing predetermined data to the defective rows of CAM cells.

Row redundancy in a content addressable memory device

A translation-lookaside buffer includes a content-addressable memory (CAM) cell to generate a CAM current signal with a first transistor configuration having a set of transistors of a predetermined size and connection. A reference current circuit generates a reference current signal with a second transistor configuration corresponding to the first transistor configuration, with the exception of the size and connection of selected transistors. A match sense amplifier selectively generates a match signal in response to the CAM current signal and the reference current signal.

Translation-lookaside buffer with current tracking reference circuit

A method and apparatus for a voltage multiplier is disclosed that includes a first stage for receiving an input voltage and a first control signal; inverting the first control signal to produce a second control signal; and outputting a first output voltage and the second control signal. The voltage multiplier also includes a second stage for receiving the first output voltage and the second control signal; and outputting a third output voltage. The first output voltage is higher than the input voltage and the second output voltage is higher than the first output voltage.

Voltage multiplier for low voltage microprocessor

A negative edge triggered flip-flop generates an output pulse in response to a negative edge of a clock signal. A first set of nodes receives data input signals, and a second set of nodes receives select input signals for selecting one data input signal as a selected data input signal. The clock node receives the clock signal which has a positive edge and a negative edge. A header circuit connects to the second set of nodes and to the clock node, and integrates the clock signal with the select input signals to generate at least one control signal. A pulse generator circuit connects to the first set of nodes, the header circuit and the output node. The pulse generator circuit generates an output pulse on the output node in response to a control signal and the selected data input signal.

Negative pulse edge triggered flip-flop

A circuit for comparing two digital words has a set of bit compare circuits that generate a set of compare signals. Each bit compare circuit receives a first bit from a first digital word and a corresponding bit from a second digital word and generates one compare signal that indicates a match between the first bit and the corresponding bit. In response to the set of compare signals, a composite match detector circuit generates a composite match signal. A last bit detector circuit generates a last bit signal that indicates a match between a last bit from the first digital word and a last bit from the second digital word. When the last bit signal is received, a match hit generator circuit generates a match hit signal based on the composite match signal and the last bit signal.

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Palo Alto, CA, United States of America

Lan Lee