Inventec Corp.

Inventec (pudong) Technology Corporation

Wuxi Mtlh Biotechnology Co., Ltd.

Lan Huang

Shih-Hao Liu

Hua Zhou

Shengtao Yuan

Crius Yang

A server system includes a baseboard management controller and calculation modules. Each calculation module includes a system on chip, slave devices and a switch. The switch is connected with the baseboard management controller, the system on chip and the slave devices. The switch issues an address selection signal to select one of the slave devices to be connected with the switch. The switch switches the baseboard management controller and the system on chip to be connected with one of the slave devices by a control signal.

Server system for switching master and slave devices

A server system having an auto-reset mechanism is provided. The server system comprises a power control circuit, a power processing circuit, a CPLD and a control circuit. The power control circuit generates a control signal. The power processing circuit operates according to the control signal to receive a first power and generate a second power. The CPLD receives the second power and operates accordingly and generates a power reset signal when the CPLD finishes a update process. The control circuit controls the power control circuit to stop to generate the control signal to turn off the power processing circuit to further disable the CPLD in a certain time period according to the power reset signal and controls the power control circuit to activate the power processing circuit to further activate and reset the CPLD after the certain time period.

Server system and auto-reset method of the same

Provided is the composition of a peptide and its mutagenic version, or other derivatives with the same 3-D structure with activity to bind the extracellular domain of PDGFR-&#x3b1;, or -&#x3b2;, but does not dimerize by itself, wherein said peptide comprises the sequence shown as SEQ ID NO: 1, 2 or 3. Also provided is the composition of the nucleotide sequence encoding said peptide and its derivatives, and the usage of said peptide and derivatives of the peptide in preparation of medicine for the prevention and treatment of fibrosis diseases, such as liver, kidney, and lung fibrosis, primary cancer, and cancer metastasis, especially stomach cancer, liver cancer, breast cancer, and lung cancer.

Pharmaceutical being used for treating cancer and fibrosis disease and the composition and uses thereof

A storage device backplane and an identification circuit for identifying using situations of the storage device backplane are provided. The storage device backplane possesses a first connection interface and a second connection interface, for being used as a first backplane supporting a motherboard, or a second backplane cascaded to the first backplane, or a first backplane supporting a daughterboard of the motherboard. The first and second backplanes possess the same storage device backplane structure. If the storage device backplane is used as the first backplane, a first connection interface of the first backplane is coupled to the motherboard or the daughterboard thereof; if the storage device backplane is used as the second backplane, a first connection interface of the second backplane is coupled to a second connection interface of the first backplane. The identification circuit identifies using situations of the storage device backplane and display corresponding correct indicator number.

Storage device backplane and identification circuit

A core voltage controlling apparatus suitable for a center processing unit (CPU) is provided. The apparatus includes a level shifting unit, a time-delay unit and a logic unit. An input terminal of the level shifting unit receives and shifts a first voltage signal, and an output terminal generates a second voltage signal, in which the first voltage signal indicates a power-on stable state, and the second voltage signal indicates a magnitude of the core voltage. The time-delay unit delays the second voltage signal to generate a third voltage signal. The logic unit is coupled to the time-delay unit for performing a logic operation on the third voltage and a fourth voltage signal transmitted by a power supply, and generating a fifth voltage signal for controlling a core voltage generator whether to provide the core voltage to the CPU or not, in which the fourth voltage signal indicates a power state.

Core voltage controlling apparatus

A power discharge control system for eliminating residual voltage of electronic components in an electronic device, is proposed, which includes a control IC for outputting first electrical signals of a first level and a second level respectively corresponding to power on and power off of the electronic device; a power supply for receiving the first electrical signal, and providing or terminating operation power to the electronic component accordingly, and delaying outputting of a second electrical signal equivalent to the first electrical signal level; a logic judgment module connected to the control IC and the power supply for receiving the first and the second electrical signals for executing logic operation process, when at least one of the first and the second electrical signals is at the first level, a third electrical signal of a third level is outputted, when both the first and the second electrical signals are at the second level, a third electrical signal of a fourth level is outputted; and at least a discharge module for receiving the third electrical signal, when the third electrical signal is at the third level, the discharge process is skipped, when the third electrical signal is at the fourth level, the discharge process is executed.

Power discharge control system

A memory reset apparatus including a first inverse circuit, a logic circuit, and a plurality of second inverse circuits is provided. The first inverse circuit receives a control signal generated by a north bridge and generates a first signal, in which the control signal controls reset of a plurality of memories. The logic circuit performs a logic operation of the first signal and an indicating signal and generates a second signal, in which the indicating signal indicates each component of a computer system completely powered on. The plurality of second inverse circuits is respectively coupled between the logic circuit and the memories. The second inverse circuits inverse the second signal and respectively generate a plurality of reset signals to the memories, so as to reset the memories.

Growing community of inventors

Shanghai, China

Lan Huang