Freescale Semiconductor,inc.

Nxp Usa, Inc.

Motorola Corporation

Other

Freescale Semiocnductor, Inc.

Lan Chu Tan

Chee Seng Foong

Wai Yew Lo

Navas Khan Oratti Kalandar

Fuaida Harun

Jinzhong Yao

Boon Yew Low

Heng Keong Yip

Kai Yun Yow

Poh Leng Eu

Xuesong Xu

Kesvakumar V C Muniandy

Chin Teck Siong

Kok Wai Mui

Kevin John Hess

Li Li

Fernando A Santos

Chu-Chung Lee

Meng Kong Lye

Zhigang Bai

Chetan Verma

Kong Bee Tiu

Cheng Qiang Cui

Hei Ming Shiu

Seng Kiong Teng

Cheng Choi Yong

Zi Song Poh

On Lok Chau

Yuan Zang

Fui Yee Lim

Viswanadam Gautham

Gor Amie Lai

Mohd Rusli Ibrahim

Lau Teck Beng

Thoon Khin Chang

Chiaw Mong Chan

Soo San Yong

Liang Jen Koh

Mohd Faizairi Bin Mohd Nor

Kee Cheong Fam

Kim Heng Tan

Bihua He

A circuit module (e.g., an amplifier module) includes a module substrate, a thermal dissipation structure, a semiconductor die, encapsulant material, and an interposer. The module substrate has a mounting surface and a plurality of conductive pads at the mounting surface. The thermal dissipation structure extends through the module substrate, and a surface of the thermal dissipation structure is exposed at the mounting surface of the module substrate. The semiconductor die is coupled to the surface of the thermal dissipation structure. The encapsulant material covers the mounting surface of the module substrate and the semiconductor die, and a surface of the encapsulant material defines a contact surface of the circuit module. The interposer is embedded within the encapsulant material. The interposer includes a conductive terminal with a proximal end coupled to a conductive pad of the module substrate, and a distal end exposed at the contact surface of the circuit module.

Circuit modules with front-side interposer terminals and through-module thermal dissipation structures

A packaged semiconductor device includes a substrate having input/output (I/O) pads, a semiconductor die attached to the substrate and electrically connected to the substrate with bond wires. A bond-wire reinforcement structure is formed over the bond wires before the assembly is covered with a molding compound. The bond-wire reinforcement structure prevents wire sweep during molding and protects the wires from shorting with other wires. In one embodiment, the bond-wire reinforcement structure is formed with a fiberglass and liquid epoxy mixture.

Semiconductor device with bond wire reinforcement structure

A 'universal' substrate for a semiconductor device is formed of a non-conductive substrate material. A uniform array of conductive pillars is formed in the substrate material. The pillars extend from a top surface of the substrate material to a bottom surface of the substrate material. A die flag may be formed on the top surface of the substrate material. Pillars underneath the die flag are connected to pillars beyond a perimeter of the die flag with wires. Power and ground rings may be formed by connecting rows of pillars that surround the die flag.

Substrate interconnections for packaged semiconductor device

A packaged IC device in which a die is sandwiched between first and second substrates such that (i) peripheral electrical contact pads of the die are wire bonded to the first substrate, e.g., for routing functional input/output signals, and (ii) core-area electrical contact pads of the die are connected to the second substrate in a flip-chip arrangement, e.g., for routing one or more power supply voltages to the core area of the die. The second substrate has a shape and position that (i) expose the peripheral electrical contact pads of the die for unencumbered machine-implemented wire bonding during the assembly process, and (ii) enable direct electrical connections between the first and second substrates outside the footprint of the die, e.g., by way of the corresponding solder bumps attached between the two substrates.

Integrated circuit package having two substrates

A semiconductor package includes a first lead frame type having a first type of package leads and a pre-molded portion, and a second lead frame type having a second type of package leads that surround a die pad and are supported by the pre-molded portion. An integrated circuit is attached to the die pad and electrically connected to the first and second types of leads with bond wires. A mold compound, which forms a mold cap, covers the first and second lead frame types, the integrated circuit and the bond wires. The first lead frame type may be a QFP type and the second lead frame type may be a QFN type.

Combined QFN and QFP semiconductor package

A circuit interconnecting substrate manufacturing method includes depositing a first layer of metallic powder on top of a carrier, and then forming a first layer of electrically conductive traces from the first layer of metallic powder. A second layer of metallic powder is then deposited onto at least one region of the first layer of electrically conductive traces. Then a second layer of electrically conductive traces is formed from the second layer of metallic powder and each trace of the second layer is electrically coupled to a trace of the first layer. An insulating material is deposited onto the carrier to provide an insulating substrate that supports the traces. The method does not require the use of any wet chemicals or chemical etching steps.

Circuit substrate and method of manufacturing same

A method of assembling semiconductor devices with semiconductor dies of alternative different configurations uses the same substrate panel. The dies of the selected configuration are placed in an array, mounted, and connected to internal electrical contact pads on a first face of the panel using main fiducial markings and an array of subsidiary fiducial markings corresponding universally to arrays of semiconductor dies of the different alternative configurations. The pitch of the subsidiary fiducial markings is equal to the spacing between adjacent rows of the internal electrical contact pads on the panel and is a sub-multiple of the pitch of the array of dies.

Substrate for alternative semiconductor die configurations

A method of making an integrated circuit package, such as a ball grid array, includes providing a flexible tape that has first and second sets of bond pads on respective first and second surfaces thereof. A carrier is attached to the first surface of the flexible tape. Then conductive pillars are formed on the second set of bond pads and an intermediate layer of polymeric compound is deposited on the second surface of the flexible tape. After the compound has cured, a surface of the intermediate layer is ground to expose ends of the conductive pillars to form a sub-assembly comprising the flexible tape and the intermediate layer. Then the carrier is removed from the sub-assembly, thereby creating an interposer. The interposer is attached to a substrate and at least one die is attached to the interposer.

Semiconductor device package with organic interposer

A semiconductor pressure sensor device having a pressure-sensing die electrically connected to a microcontrol unit (MCU) using either through silicon vias (TSVs) or flip-chip bumps. An active surface of the pressure-sensing die is in facing relationship with the MCU. These embodiments avoid the need to used bonds to electrically connect the pressure-sensing die to the MCU, thereby saving time, reducing size, and reducing cost.

Pressure sensor device with through silicon via

An interposer for a packaged semiconductor device is formed by applying an encapsulant to (e.g., by overmolding or applying lamination of tapes to) a perforated metal foil having vertical metal tabs that form the vertical metal vias in the interposer. A solid metal foil can be stamped using a micro-stamping tool to form the perforated foil and vertical tabs. Bump pads and/or re-distribution layer (RDL) traces are formed (e.g., using wafer fabrication processes or by applying flexible tape RDL layers) on the top and back sides of the foil to complete the manufacturing process. Such interposers can be cheaper to manufacture than conventional interposers having silicon or glass substrates with through-silicon vias (TSVs) formed using wafer fabrication processes.

Interposer with overmolded vias

A pressure sensor device includes a gel retainer that is mounted or formed on a substrate. The gel retainer has a cavity and a pressure sensing die is mounted inside the cavity. The die is electrically connected to one or more other package elements. A pressure-sensitive gel material is dispensed into the cavity to cover an active region of the pressure sensing die. A mold compound is applied on an upper surface of the substrate outside of the gel retainer.

Pressure sensor device with gel retainer

A packaged semiconductor device has an integrated circuit (IC) die and first and second volumes of molding compound. The first volume of molding compound is disposed on a first portion of a first side of the IC die and comprises a first molding compound. The second volume of molding compound is disposed on a second side of the IC die, different from the first side, and comprises a second molding compound, different from the first molding compound. By including different molding compounds, the properties of the packaged semiconductor device can be varied across the device.

Non-homogeneous molding of packaged semiconductor devices

A semiconductor device includes a semiconductor die encapsulated in a package casing and having four main side walls each oriented generally parallel with one of first or second orthogonal directions. Signal leads are electrically coupled to the die and each has an exposed portion that extends from one of the main side walls parallel with one of the first or second directions. One or more power bars are electrically coupled to the die and each has at least one power bar lead extending at a non-zero angle with respect to the first and second directions. The power bars and associated power bar leads are electrically isolated from the signal leads. One or more tie bars extends at a generally non-zero angle with respect to the first and second directions and is electrically isolated from the signal leads and the power bars and associated power bar leads.

Power bar design for lead frame-based packages

A method of attaching a bond wire to first and second electrical contact pads includes holding the bond wire in a capillary, wherein a first end of the bond wire extends out of an opening in the capillary, attaching the first end of the bond wire to the first electrical contact pad using a ball bonding technique, moving a second end of the bond wire toward the second electrical contact pad after the attachment of the first end of the bond wire, performing an electric flame off on the second end of the bond wire without forming a free air ball, and attaching the second end of the bond wire to the second electrical contact pad after the EFO on the second end of the bond wire.

Insulated wire bonding with EFO before second bond

A pillar bump, such as a copper pillar bump, is formed on an integrated circuit chip by applying a metallic powder over a conductive pad on a surface of the chip. The metallic powder is selectively spot-lasered to form the pillar bump. Any remaining unsolidified metallic powder may be removed from the surface of the chip. This process may be repeated to increase the bump height. Further, a solder cap may be formed on an outer surface of the pillar bump.

Pillar bump formed using spot-laser

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Singapore, Singapore

Lan Chu Tan