Xerox Corporation

General Instrument Corporation

Lamar T Baker

Steven A Buhler

Mostafa R Yazdy

George K Tu

Scott Alan Elrod

Babur B Hadimioglu

Abdul M ElHatem

George E Mager

Jaime Lerma

Robert E Markle

Richard G Stearns

Joy Roy

William F Gunning

Richard B Rubinstein

Abdul M El Hatem

An electronic driver circuitry for an RF switch diode used in Acoustic Ink Jet Printing (AIP) systems is disclosed The electronic driver circuitry consists of a PMOS transistor and a poly resistor used to control the on/off states of the RF switch diode wherein the drive current for the RF switch diode is the same as the current in the PMOS transistor. To compensate for undesirable variations in the RF switch diode, the driver circuitry is designed such that the current in the PMOS transistor is adjusted in an opposite direction to cancel the unwanted variations.

Process insensitive electronic driver circuitry for integrated RF switching diodes

A number of architectures of switch compensation networks are described for the provision of a compensation current which ensures the maintaining of a desired switching ratio in an acoustic printhead. The described architectures include those which provide column compensation, row compensation, and row and column compensation to a transducer switching matrix. Control of the switching ratio by the compensation networks, is used in consideration of the dissipation of heat energy through expulsion of a heated drop, to provide a precisely controlled balance.

Method and apparatus for achieving controlled RF switching ratios to maintain thermal uniformity in the acoustic focal spot of an acoustic ink printhead

Described are various compensation circuit designs to ensure proper shutoff of an unselected transducer in a transducer switching matrix. The switch of an unselected transducer is moved to a strong OFF state by injection of a compensation current. The compensation network is implemented as semiconductor integrated circuits which provide a high-voltage column switching diode, and a compensation switch. The compensation switch and column switching diode are configured such that they are isolated from each other.

Printhead array compensation device designs

A method and apparatus for controlling power delivered from a power source to droplet sources in a printer is described. The described system uses a compensation value corresponding to each droplet source to compensate for differences between droplet sources. By using the compensation value to adjust the power delivered to each droplet source on a print head, a uniform droplet size is obtained from all droplet sources on the print head.

Method and apparatus to provide adjustable excitement of a transducer in a printing system in order to compensate for different transducer efficiencies

An acoustic inkjet printhead utilizes a pulse width modulation to control droplet size or ejection velocity. An individual control pulse controls the duration and the time a RF signal is applied to each transducer. To modify the RF signal of each transducer, the pulse width of each control signal can be modified according to a predetermined correction data. The rising edge of the control data is delayed according to the correction data while the falling edge is kept the same.

Pulse width modulation for correcting non-uniformity of acoustic inkjet printhead

For use in a microprocessor on a single semiconductor chip, a circuit responsive to first and second non-overlapping time signals for removing timed delay in a first data line. A first enhancement-type field effect device has its drain coupled to the first data line and its gate providing an input for the first timing signal. A second enhancement-type field effect device has its drain coupled to the source of the first device and its source coupled to a source voltage. The source voltage is at ground potential. A third enhancement field effect device has its drain coupled to the first data line, its source coupled to the gate of the second device, and its gate providing an input for the second timing signal.

Time slot end predictor

A mask programmable logic array (PLA) for producing a particular digital output given a certain digital input. The input signals to the PLA first pass through a series of AND gates resulting in a predetermined number of product terms being formed. The product signals then pass through a set of OR gates to become the final output signals. In the subject invention, the AND gates and OR gates are implemented through the use of NOR-NOR logic. A first set of NOR gates is implemented in an array to receive input signals and to produce product terms. A second and third set of NOR gates form two arrays. These two arrays are then located on either side of the first array to receive selected product signals in order to produce final output signals. In effect the OR portion of the PLA has been split into two arrays.

Split programmable logic array

Word select circuitry which eliminates double RAM row addressing is used with a read-write memory system of the type employing a plurality of word select lines. Sample and latch devices store input memory address data sampled at a predetermined rate. The devices provide at their outputs the stored data and its complement until new input memory address data is sampled. Additional circuitry is provided for producing a sampling signal which causes the latch devices to sample the input memory address data at the predetermined rate. A decoder provides signals to activate a selected one of the word select lines in response to the data signals received from the outputs of the latch devices. Additional circuitry is coupled to the decoder to produce a signal which precludes the activation of all of the word select lines when the latch devices are sampling input memory address data. In the preferred embodiment, all of the aforementioned circuitry is contained on a single semiconductor chip. In addition, a timing device on the chip is provided for synchronizing the data flow in the memory system.

Circuitry for eliminating double ram row addressing

The chip topography of an MOS microprocessor chip. The chip architecture includes an internal data bus and an internal address bus. Input/output circuitry is located along the top edge of the chip and is coupled to the data bus. Output circuitry is located along the bottom edge and coupled to the address bus. A program storage area which includes a ROM is located in the lower left hand corner of the chip. The ROM contains instruction words for defining the operation of the microprocessor. A data storage area which includes a RAM is located in the upper left hand corner of the chip and is coupled to the data bus. An ALU area is located to the right of the data storage area and is coupled to the data bus for performing arithmetic and logic operations on data. A condition decode ROM located in the approximate center of the chip is coupled to the data bus and is used for decoding a condition field of an instruction word received from the ROM. A bus control area is located in the upper right hand corner of the chip. A programmed control area is located between the ALU area and the bus control area in the upper right hand portion of the chip and is coupled to the data bus for receiving instruction words from the program storage area and for generating commands which define the operation of the microprocessor in response to the instruction words. A clock/T-counter is located in the lower right hand corner and is used for synchronizing data signal flow in the micrprocessor. A stack area is located in the lower right hand portion of the chip. Within this stack area are various registers located from top to bottom as follows; write X circuitry, an X register a stack array, stack read/write circuitry, a memory address register, and an incrementer. A stack control is located between the aforementioned stack circuitry and the right hand edge. In addition, a RAM decode is located between the RAM and the left hand edge, a ROM column decode is located between the ROM and the bottom edge, and a ROM row decode is located between the ROM and the stack area.

Chip topography for MOS integrated circuitry microprocessor chip

For use in a microprocessor on a single semiconductor chip, circuitry responsive to a timing signal and a data signal for discharging a precharged data line to correspond to the data to be transmitted on the data line. First and second enhancement-type field effect devices are connected in series with the drain of the first device being connected to the data line and the source of the second device being connected to a source voltage. The gate of one of the field effect devices provides an input for the timing signal. The gate of the remaining field effect device provides an input for the data signal. A depletion-type field effect device has its source and gate coupled to the series connection point and its drain connected to a drain voltage source. The depletion-type field effect device prevents a charge redistribution from the data line to the series field effect devices when these devices are not discharging the line.

Precharged data line driver

A random access memory (RAM) containing 256 memory cells organized as two pages, each page containing 16 8-bit wide working registers. RAM row address circuitry as well as read-write and page-select circuitry are provided. A fixed transistor static RAM cell is used as the memory cell. Double rail transfer of data is employed. The memory cells and bit lines associated with each of the two pages is interweaved in the array so that the precharged circuitry and the RAM input/output circuitry associated with each of the pages is alternately configured on the chip.

Two-page interweaved random access memory configuration

A MOS control circuit for controlling an output signal, said control circuit being coupled to first and second sources of potential. The magnitude or peak-to-peak amplitude of the first source of potential is greater than the magnitude developed by the second source of potential. The control circuit output signal has a waveshape magnitude of desired dimension somewhere between the magnitude of the second source of potential and the magnitude of the first source of potential. In order to accomplish this, a first inverter receives and inverts an input signal and produces an output potential at a node. A clamping circuit reduces the potential at the node by a desired amount. A source follower is driven by the potential at the node and also receives the input signal. The output of the source follower is the control output signal.

MOS buffer circuit

An integrated circuit ram amplifier includes a feedback loop which produces an output pulse before the output from the random access memory has completed its transition from full voltage to ground, thus increasing the computer's response time. The integrated circuit amplifier may find particular application in microprocessors (e.g. 8 bit word length, single bus two phase clock microprocessors).

Growing community of inventors

Manhattan Beach, CA, United States of America

Lamar T Baker