Samsung Electronics Co., Ltd.

Qualcomm Incorporated

Lam Van Nguyen

Chiaming Chai

Jeffrey Herbert Fischer

Stephen Edward Liles

Andrew Joseph Dickerson

Shaoping Ge

James Edward Van Den Heuvel

Alexander Gregory Chu

Jiyoon Park

Liang Dai

Quan Van Nguyen

Michael Butler

Seungjun Hyun

Sophie Kim

Chris Goodman

Jaemin Joo

Jeff Wilkinson

Kitae Kim

James Edward Vandenheuvel

Jordan Daniel Goulding

Euihwa Noh

Yilee Seo

Tom Min-Tien Chen

Quan Nguyen

According to an aspect of the disclosure, a method for displaying content on a display of an electronic device comprises determining, based on information about the content, a first region of the display on which a first portion of the content is to be displayed; obtaining an angle between the first region and a second region of the display, the second region being distinguished from the first region; generating, based on the angle and a location of a user, correction content corresponding to a second portion of the content; and displaying the first portion on the first region, and displaying the correction content on the second region.

Method and apparatus for displaying content on display

An apparatus, a method, a method of manufacturing and apparatus, and a method of constructing an integrated circuit are provided. The apparatus includes a reservation logic device that receives a plurality of primitive types in a data pipeline, wherein the plurality of primitive types includes a binning (BIN) primitive and a setup (SU) primitive; a combinatorial logic device connected to the reservation logic device; an allocation logic device connected to the combinatorial logic device; a plurality of BIN buffers connected to the reservation logic device and the allocation logic device; and a plurality of SU buffers connected to the reservation logic device and the allocation logic device, wherein the allocation logic device determines whether a primitive type is allocated to a BIN buffer or a SU buffer, wherein the reservation logic device requests a reservation of one of the plurality of BIN buffers and the plurality SU buffers based on a corresponding indication of available BIN buffers and available SU buffers and the primitive type.

Apparatus and method for speculative buffer reservations with cancellation mechanism

A clip-cull-viewport (CCV) unit manages information associated with vertices of a primitive as the primitive passes through the CCV unit. The CCV unit includes an index cache and a cache-status table. Vertices of a received primitive are stored in locations within the index cache based on attribute and index fields of the primitive. If a vertex is a reused vertex of another primitive that matches a valid entry in the cache-status table and if the primitive survives being culled, the valid entry in the cache-status table is preserved, the attribute field of the primitive is set to indicate that the vertex is a reused vertex, and the primitive is sent to an output interface for a downstream unit. Otherwise, the attribute field is set to indicate that the vertex is not reused, and the primitive is sent to the output interface for the downstream unit.

System and method for cache management using a cache status table

A method and system is provided for using a split screen mode. The method includes composing a plurality of surfaces into a final surface to display in a display unit of a user equipment. The display unit is operable to display a single screen mode and a split screen mode. The method also includes, responsive to identifying the split screen mode, splitting the display unit into a first screen and a second screen. The method also includes retrieving a set of parameters associated with the split screen mode. The method also includes displaying the final surface in both the first screen and the second screen according to the set of parameters.

Apparatus and method for split screen display on mobile device

A method is provided for creating a single interactive video file. The method includes receiving a selection of a plurality of 360-degree videos including a first 360-degree video and a second 360-degree video. The method also includes linking the first 360-degree video to the second 360-degree video to enable transitioning between the first 360-degree video and the second 360-degree video. The method also includes compiling the plurality of 360-degree videos into the single interactive file. The single interactive video file includes an index used to identify the second 360-degree video within the single interactive video file when the link is executed.

System and method for interactive 360-degree video creation

Display screen or portion thereof with graphical user interface

Systems and methods for adaptively mimicking wordline decoding logic for multi-voltage domain memory are disclosed. In one embodiment, the multi-voltage domain memory includes a memory array implemented in a high voltage domain and a multi-voltage domain control circuit. The multi-voltage domain control circuit includes multi-voltage domain decoding logic that generates a wordline for the memory array and a multi-voltage domain mimic logic that mimics the multi-voltage domain decoding logic to generate a dummy wordline. In one embodiment, the dummy wordline is utilized to trigger an ending edge (e.g., a falling edge) of the wordline once the wordline is asserted. In addition or alternatively, the dummy wordline is utilized to generate one or more control signals for the memory array such as, for example, a pre-charge control signal and/or a sense amplifier enable signal.

Mimicking multi-voltage domain wordline decoding logic for a memory array

Systems and methods for generating pulse clocks with programmable edges and pulse widths configured for varying requirements of different memory access operations. A pulse clock generation circuit includes a selective delay logic to provide a programmable rising edge delay of the pulse clock, a selective pulse width widening logic to provide a programmable pulse width of the pulse clock, and a built-in level shifter for shifting a voltage level of the pulse clock. A rising edge delay for a read operation is programmed to correspond to an expected read array access delay, and the pulse width for a write operation is programmed to be wider than the pulse width for a read operation.

Pulse clock generation logic with built-in level shifter and programmable rising edge and pulse width

A duty cycle correction circuit capable of generating a clock signal having good (e.g., approximately 50%) duty cycle is described. The duty cycle correction circuit includes a clock deskew circuit and a duty cycle detection circuit. The clock deskew circuit receives an input clock signal that may have poor duty cycle, adjusts the input clock signal based on a control, and provides an output clock signal having an adjustable duty cycle. The duty cycle detection circuit detects error in the duty cycle of the output clock signal and generates the control in response to the detected error in the duty cycle. The clock deskew circuit and the duty cycle detection circuit implement a feedback loop that senses error in the duty cycle of the output clock signal and feeds back the control to correct the duty cycle error.

Duty cycle correction circuit

A dummy SRAM cell for use in a dummy bit line circuit uses the same transistors as used in a standard SRAM cell, which includes first and second subsets of transistors configured as first and second bit line output circuits. The dummy SRAM cell includes the same first and second subsets of transistors, with the first transistors configured as a dummy bit line output circuit having substantially the same electrical characteristics as the first bit line output circuit of the standard SRAM cell. Further, the second transistors, which are not otherwise needed for the dummy SRAM cell function, are reconfigured as a voltage tie circuit for the dummy bit line output. Using the second transistors for this purpose obviates the need to add additional transistors to form a voltage tie circuit for configuring the dummy bit line output circuit as a load or driver for the dummy bit line.

Method and apparatus for a dummy SRAM cell

Growing community of inventors

Cupertino, CA, United States of America

Lam Van Nguyen