Qualcomm Incorporated

Atheros Communications, Inc.

Qualcomm Atheros Inc.

Lalitkumar Nathawad

Shahram Abdollahi-Alibeik

Mohammad Bagher Vahid Far

Abbas Komijani

James M Gardner

Ali Agah

Tevfik Yucek

Alireza Khalili

Yashar Rajavi

Amirpouya Kavousian

David J Weber

Masoud Zargari

Sarvesh Shrivastava

Hyunsik Park

Justin A Hwang

Patrick Kelliher

Mohammad Mahdi Ghahramani

Manoj Unnikrishnan

Burcin Baytekin

Suresh Chandrasekaran

Ke Gong

Alireza Kheirkhahi

Felix Bitterli

Christopher Pisz

Mani Krishnan Venkatachari

A method and apparatus are disclosed for a wireless communication device capable of scanning for radar signals while detecting and/or receiving a wireless communication signal. The wireless communication device may include a plurality of local oscillator synthesizers to allow distinct frequency bands to be used for wireless communication signals and radar detection. In some embodiments, the wireless communication device may include a radar detection physical layer (PHY) circuit to detect the presence of radar signals within a received RF signal. The radar detection PHY may have limited functionality suitable primarily for radar signal analysis and not suitable for processing (decoding) communication signals.

Agile radar detection for wireless communications

A multi-band amplifier may operate in a first frequency band and a second frequency band. The multi-band amplifier may include a first amplifier, a second amplifier, and a coupler. The coupler may couple a signal, such as a communication signal, to a selected amplifier. In some embodiments, the coupler may include one or more inductive elements to couple the signal to the first or the second amplifier. In some embodiments, the inductive elements may include a balun.

Multi-band amplifier

A wireless communications device that produces phase-synchronized local oscillator (LO) signals. The device includes a first transceiver chain to receive a first timing signal and a second transceiver chain to receive the first timing signal and a second timing signal. The first transceiver chain includes a first frequency divider to convert the first timing signal to a first LO signal. The second transceiver chain includes a multiplexer to select one of the timing signals based at least in part on a mode select signal. A second frequency divider in the second transceiver chain converts the selected timing signal to a second LO signal, and a phase alignment circuit aligns a phase of the second LO signal with a first alignment signal. The first alignment signal is activated, for a limited duration, in response to a change in state of the mode select signal.

Multi-chip TX beamforming for per-packet switching with reduced LO leakage

This disclosure describes techniques for providing active interference cancellation in a wireless communication system having a Bluetooth transmit chain and a WLAN receive chain. A signal sampled from the Bluetooth transmit chain is gain and phase adjusted to offset interference in the WLAN receive chain. A quadrature phase shifter may be used to generate quadrature components of the sampled signal that are selectively combined to achieve a desired phase adjustment. The phase shifter may be stabilized by a variable capacitor. These techniques may be extended to MIMO systems.

Systems and methods for active interference cancellation to improve coexistence

In a serial communication system having a device including a receiver detection module, this specification is directed to systems and methods for selectively reducing the power consumed by the receiver detection module, preferably when the device is operating in a low power mode. In some embodiments, a signal detection module is configured to receive a control signal from the transmitter of a device at the other end of the communications link to control the operation of the receiver detection module. The control signal may be in-band or may be transmitted on a sideband of the serial link.

System and method for standby power reduction in a serial communication system

Integrated circuits are disclosed including at least one inductor-capacitor component, where each of the inductor-capacitor components includes an inductor and a capacitor constructed between the inductor and a substrate. The inductor includes at least one metal loop over a shield pattern forming a first capacitor terminal over patterned oxide layer with a second capacitor layer between the patterned oxide layer and the substrate.

Patterned capacitor ground shield for inductor in an integrated circuit

A digital regulated Local Oscillator (LO) buffer receives an unregulated LO signal from a local oscillator to create a regulated LO signal. Embodiments include not only the digital regulated LO buffer, but also a transceiver and/or a receiver including at least one instance of the digital LO buffer. They may be implemented as an integrated circuit. The digital regulated LO Buffer may include: A LO buffer receiving the unregulated LO signal and an amplitude control signal to create the regulated LO signal. A peak detector receives the regulated LO signal to create an analog peak signal that is presented to a digital output comparator along with a reference amplitude signal to create a digital threshold detect signal. An amplitude controller receives the digital threshold detect signal to create a digital control signal that drives a digitally controlled source to create the amplitude control signal.

Method and apparatus for a digital regulated local oscillation (LO) buffer in radio frequency circuits

A technique for improving frequency synthesizer performance by frequency-compensating charge pump current in order to maintain a consistent loop bandwidth over a wide operating frequency range is described. A relationship between the capacitance value associated with a voltage controlled oscillator resonant tank and the magnitude of current pulses in a related charge pump is exploited to bound the loop bandwidth of the frequency synthesizer over both operating frequency and process variation. A control state machine generates digital coarse tune values that dynamically select a capacitance for the resonant tank, such that the voltage controlled oscillator operates within an optimal control voltage range. Each dynamically selected capacitance value is then used to determine the magnitude of current pulses in the charge pump.

Charge pump current compensation for phase-locked loop frequency synthesizer systems

A phase frequency detector comprising a detection circuit and a reset circuit. The phase frequency detector may receive a feedback signal having a predetermined pulse width. The detection circuit may generate a first control signal based on a reference signal, and a second control signal based on the feedback signal. The reset circuit may generate a reset signal used for resetting the detection circuit based on the first control signal, the second control signal, and the feedback signal. The feedback signal may be tied to the generation of the reset signal such that, during a locked state, the pulse width of the second control signal is approximately equal to the pulse width of the feedback signal, which helps reduce the sensitivity of the circuit to nonlinearities.

Phase frequency detector with pulse width control circuitry

A voltage-controlled oscillator (VCO) comprising a first circuit, a second circuit, a comparator circuit, and a control unit. The first circuit can determine an output common mode voltage associated with an output of the VCO. The second circuit can generate an upper control voltage limit and a lower control voltage limit associated with a control voltage received by the VCO based, at least in part, on the output common mode voltage. The comparator circuit can compare the control voltage to the upper and lower control voltage limits. The control unit can determine whether to change a switched capacitance associated with the VCO based, at least in part, on whether the control voltage is outside the upper and lower control voltage limits, thereby maintaining an optimal region of operation for the control voltage.

Voltage-controlled oscillator with control range limiter

An interleaved ADC can advantageously provide synchronous sampling and time-multiplexed output. Differential I and Q input signals can first be stored by charging a plurality of capacitors. These stored differential signals can be buffered in a time-multiplexed sequence. For example, buffering can include transferring voltages stored by a first set of capacitors at a first time and then transferring voltages stored by a second set of capacitors at a second time. Advantageously, this time-multiplexing allow the ADC to be significantly smaller than conventional implementations of two-input ADCs. A folded mixer with gain control is also provided. This mixer can include a first stage having a first set of inductors and a plurality of first type transistors and a second stage having a second set of inductors and a plurality of second type transistors. The plurality of second type transistors in the second stage, which are in a folded configuration, can be driven by the first set of inductors in the first stage. The outputs of the mixer are positioned between the plurality of second type transistors and the second set of inductors. This configuration advantageously permits the mixer to use a low operating voltage.

Growing community of inventors

Pleasanton, CA, United States of America

Lalitkumar Nathawad