Samsung Electronics Co., Ltd.

Lalitkumar Motagi

Matthew S Berzins

Shyam Agarwal

A low-power low-setup integrated clock gating (ICG) cell is disclosed. The disclosed ICG cell includes a NOR gate configured to receive an enable (E) signal and a test enable (SE) signal, and to output an EN signal. The ICG cell may include a complex gate configured to receive the EN signal and a clock (CK) signal, and to output a latched enable (ELAT) signal. The ICG cell may further include a NAND gate configured to receive the ELAT signal and the CK signal, and to output an inverted enabled clock (ECKN) signal. The ICG cell may further include an inverter configured to receive the ECKN signal from the NAND gate, and to output an enable clock (ECK) signal.

Low-power low-setup integrated clock gating cell with complex enable selection

According to one general aspect, an apparatus may include a latch circuit configured to, depending in part upon a state or at least one enable signal, pass a clock signal to an output signal. The latch circuit may include an input stage controlled by the clock signal and the enable signal(s). The latch may include an output stage configured to produce the output signal. The input and output stages may share a common transistor controlled by the clock signal.

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Austin, TX, United States of America

Lalitkumar Motagi