Gte Laboratories Incorporated

Lalit Patel

Michael Cooperman

Richard W Sieber

Donald J Gray

Arnold H Bearak

Shou-I Wang

A digital switching system is described for providing time division multiplexed digital communication of parallel sequential signals of N words each of M bit length between N telephone data subscribers over N transmission lines in which an array of orthogonal RAM memory devices provide parallel-to-serial conversion and multiplexing of the N words each of M bit length to provide a time division multiplexed serial digital bit stream of M words, each N bits in length, which are transmitted over a transmission line to a serial-to-parallel converter and coupled to a second orthogonal RAM memory device in which the N words M bits in length from the serial-to-parallel converter are stored and coupled to N telephone data subscribers over the transmission lines.

Digital switching system with two-directional addressing rams

Programmable logic arrays can be formed utilizing emitter coupled logic. Input terminals and control terminals associated with a programmable logic array module are coupled to the input terminals of a predetermined set of OR circuit means within the module. The outputs of the OR circuit means are coupled to various input terminals of a number of AND gates within the module. The outputs of the AND gates are coupled respectively to output terminals associated with the programmable logic array. The OR circuit means and the AND gates are coupled together in an emitter coupled logic format.

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Billerica, MA, United States of America

Lalit Patel