Nvidia Corporation

Lalit Gupta

Jesse S Wang

Stefan P Sywyk

Andreas J Gotterba

Jason Golbus

Ka Yun Lee

Karan Gupta

Amy Chen

Jesse San-Jey Wang

Ramya Challa

Kirk Twardowski

Chad Parsons

The disclosure introduces a level-shifter including a boost circuit that provides a 'one-shot' pulse (a self-annihilating pulse) with the transitioning edge of the output signal. The pulse can be used to produce a faster output rise time and reduce the overall footprint of a level-shifter compared to conventional level-shifters. In one example the level-shifter includes: (1) input circuitry configured to receive one or more input signals from one or more input voltage domains, (2) output circuitry configured to provide an output signal, based on at least one of the one or more input signals, for an output voltage domain, wherein an operating voltage of the output voltage domain is greater than an operating voltage of the one or more input voltage domains, and (3) a boost circuit connected to the output circuitry and configured to provide a current pulse for a transition edge of the output signal.

Level-shifter having a wide operating range, a fast output fall delay and improved rise time

Mechanisms to mitigate signal race conditions in circuits that utilize multiple voltage domains. The mechanisms are applicable in signal fanout scenarios where leakage becomes problematic to signal timing, such machine memory devices, e.g., volatile single port or multi-port memory devices such as SRAMs (volatile static random access memory) or other bit-storing cell arrangements that include memory cells and a hierarchical bitline structure including local bitlines for subsets of the memory banks and a global bitline spanning the subsets.

Contention-free dual-voltage logic cell

The disclosure provides improvements for transmitting data between different voltage domains of an IC, such as a chip. The disclosure introduces a data transfer circuit that uses a multi-voltage RAM, referred to herein as MVRAM, for transmitting data across the different voltage domains. The MVRAM has multiple memory cells with write ports and read ports on different clock and voltage domains. Accordingly, a write operation can occur completely on the write domain voltage and the read operation can occur completely on the read domain voltage. In one example, the data transfer circuit includes: (1) write logic operating at a first operating voltage, (2) read logic operating at second operating voltage, and (3) a MVRAM with write ports that operate under the first operating voltage and read ports that operate under the second operating voltage.

Multi-voltage RAM used to cross clock and voltage domains

A static random access memory (SRAM) or other bit-storing cell arrangement includes memory cells and a hierarchical bitline structure including local bitlines for subsets of the memory banks and a global bitline spanning the subsets. A keeper circuit for the global bitline is replaced by bias circuitry on output transistors of the memory cells.

Keeper-free volatile memory system

To mitigate pulse shape degradation along a signal route, the signal is driven from two ends. One end of the route is loaded and the other is relatively unloaded. The loaded route and unloaded route may traverse two different metal layers on a printed circuit board. The two routes may thus be related such that the unloaded route has less RC distortion effects on the signal than does the loaded route.

Slew signal shaper circuit using two signal paths

A machine memory includes multiple memory cells. Word lines, each with at least one word line driver, are coupled to the memory cells along rows. The word line drivers of at least some adjacent pairs of the word lines are coupled together by a pull-down transistor, in a manner that reduces read disturb of the memory cells.

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Fremont, CA, United States of America

Lalit Gupta