Analog Devices,inc.

Lalinda D Fernando

Baozhen Chen

Michael C Coln

Michael C W Coln

Micah Galletta O'Halloran

Zhichao Tan

Andrew Wayne Shaw

Frank M Yaul

A self-routing capacitor for an integrated circuit having: a first electrode comprising a first base region and a first finger, the first finger extending from a wall of the first base region in a first direction; a second electrode comprising a second base region and a second finger; the second finger extending from a wall of the second base region in a second direction substantially parallel to and opposing the first direction, the second finger coupled to the first finger; a third electrode comprising a third base region and a third finger, the third finger extending from a first wall of the third base in the second direction; and a fourth electrode comprising a fourth finger, the fourth finger extending from a second wall of the third base region in the first direction. The capacitor being coupled to other metal layers through a base region of an electrode.

High density self-routing metal-oxide-metal capacitor

A method of performing analog-to-digital conversion using a successive approximation (SAR) analog-to-digital converter (ADC). A previous digital output is compared to a range based on the first M bits of the previous digital output. If the previous digital output is within that range, a digital-to-analog converter (DAC) of the SAR ADC is preloaded with the first M bits of the previous digital output, prior to commencing bit trials. If the previous digital output is outside of that range, an offset is applied to the first M bits of the previous digital output and the DAC is preloaded based on the M bits and the offset, prior to performing bit trials. This method reduces the possibility of the next input being outside of a further range defined by the preload.

Method of performing analog-to-digital conversion

A self-adaptive SAR ADC techniques that can increase speed and/or decrease its power consumption. In some example approaches, one or more bits from a conversion of a previous sample of an analog input signal can be preloaded onto a DAC circuit of the ADC. If the preloaded bits are determined to be acceptable, bit trials on the current sample can be performed to determine the remaining bits. If not acceptable, the ADC can discard the preloaded bits and perform bit trials on all of the bits. The self-adaptive SAR ADC can include a control loop to adjust, e.g., increase or decrease, the number of bits that are preloaded in a subsequent bit trial using historical data.

Self-adaptive analog-to-digital converter

In an example, a successive approximation register analog-to-digital converter includes a switched capacitor digital-to-analog converter (DAC) first array to sample an input signal and to convert a sample of the input signal to a digital value represented by a plurality of bits, the first array including a first group of capacitors representing at least some of the plurality of bits, a switched capacitor DAC second array including a second group of capacitors representing at least some of the plurality of bits, wherein at least one bit of the plurality of bits represented by the second group of capacitors is represented by at least two capacitors, and wherein each of the two capacitors is configured to be selectively connected to a selected one of at least two reference potentials such that the at least one bit represented by the second group of capacitors is switchable between at least three states.

Techniques for reducing offsets in an analog to digital converter

Apparatus and methods calibrate one or more gain ranges for errors. A system can identify offset error and amplification error that occurs when the system transitions from amplifying an input signal by a first gain factor to amplifying the input signal by a second gain factor. To identify the amplification error, the system can compare the slope of the data signal in a source or reference gain range with the slope of the data signal in the destination gain range. To identify the offset error, the system can compare the amplitude of the data signal in a destination gain range with an expected value in the destination gain range.

Gain calibration

The present disclosure provides for split-path data acquisition chains and associated signal processing methods. An exemplary integrated circuit for providing a split-path data acquisition signal chain includes an input terminal for receiving an analog signal; an output terminal for outputting a digital signal; and at least two frequency circuit paths coupled with the input terminal and the output terminal, wherein the at least two frequency circuit paths are configured to process different frequency components of the analog signal and recombine the processed, different frequency components, thereby providing the digital signal.

Split-path data acquisition signal chain

An interface system between an RDC and a connected resolver dynamically matches an input range of the RDC to the output range of the resolver's output signals. The interface system may include methods and/or apparatuses to determine the amplitude of sinusoidal input signals presented to the RDC by the resolver and to compare the amplitude against high and low threshold values. A gain control signal may be generated, which may be corrected if the detected amplitude either exceeds the high threshold or falls below the low threshold. The gain control signal may be output to a circuit in the RDC or in the resolver that corrects any mismatch that occurs between the RDC input and the resolver output. For example, the gain control signal may control the amplitude of an excitation signal applied to a primary of the resolver or the gain control signal may be applied to an analog to digital converter at the input of the RDC to control its effective input range.

Signal amplitude adjustment to improve resolver-to-digital converter performance

A system and method for reducing noise in resolver-to-digital converters (RDC) using a cascaded tracking loop filter. In some embodiments, one or more tracking loop filters may be implemented in a cascade to attenuate carrier harmonic frequencies in the digitized output of an RDC. Where a plurality of tracking loop filters are implemented, the output of one tracking loop filter may be input into a successive tracking loop filter.

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Westford, MA, United States of America

Lalinda D Fernando