Intel Corporation

Lakshminarayana Pappu

Abhishek R Appu

Suketu U Bhatt

Baruch Schnarch

Amit Kumar Srivastava

Robert P Adler

Timothy J Callahan

Hem Doshi

Satheesh Chellappan

Robert Milstrey

James J Grealish

Altug Koker

David J Harriman

Murali Ramadoss

Joydeep Ray

Elmoustapha Ould-Ahmed-Vall

Subramaniam M Maiyuran

Varghese George

Ankur N Shah

Nicolas C Galoppo Von Borries

Aravindh V Anantaraman

Christopher E Cox

Nausheen Ansari

Navneet Dour

Ramadass Nagarajan

Christopher J Nelson

Mahesh S Natu

Pete D Vogt

Mike MacPherson

Howard L Heck

Valentin Andrei

Hooi Kar Loo

Robert De Gruijl

R Selvakumar Raja Gopal

Rahul Pal

Todd M Witter

Dongsheng Bi

Israel Diamand

Kalyan C Kolluru

Asaf Rubinstein

Phani Kumar Kandula

Tomer Levy

Uddalak Bhattacharya

Kah Meng Yeem

Ki W Yoon

Guadalupe J Garcia

Yuen Tat Lee

Mahak Gupta

Amande B Trang

Yonah Lasker

Rius Tanadi

Danka Goldin Schwabova

Robert D Adler

Ali Ibrahim

Rahul Joshi

Shrikul Atulkumar Joshi

Abhishek Reddy Pamu

Naveen Kanumuri

In one embodiment, a device includes: an interface circuit to couple the device to a host via a link, where in a first mode the interface circuit is to be configured as an integrated switch controller and in a second mode the interface circuit is to be configured as a link controller; and a fabric coupled to the interface circuit, the fabric to couple to a plurality of hardware circuits, where the fabric is to be dynamically configured for one of the first mode or the second mode based on link training of the link. Other embodiments are described and claimed.

System, method, apparatus and architecture for dynamically configuring device fabrics

Embodiments relate to a controller subsystem that includes a virtual reality (VR) subsystem to: identify data received from a peripheral device as related to an audio/visual (A/V) function of the peripheral device; direct, based on the identification that the data is related to the A/V function of the peripheral device, the data to be stored in a memory subsystem of the controller subsystem; and facilitate transmission of an indication of a storage location of the data in the memory subsystem to a host system that is communicatively coupled with the controller subsystem. The controller subsystem further includes a graphics engine to: identify, in a message received from the host system based on the transmission of the indication of the storage location of the data, instructions related to rendering the data; and generate, based on the data received from the peripheral device, rendered data. Other embodiments may be described and claimed.

Low latency communication path for audio/visual (A/V) applications

An apparatus comprises a first tile comprising a first instance of a plurality of global endpoints and a first instance of a plurality of local networks comprising a plurality of local endpoints; and an interconnect network of the first tile to couple to an interconnect network of a second tile, the second tile comprising a second instance of the plurality of global endpoints and a second instance of the plurality of local networks comprising the plurality of local endpoints; wherein the interconnect network utilizes an address space comprising unique identifiers for the plurality of global endpoints of the first and second tiles; and non-unique identifiers for the plurality of local endpoints of the first and second tiles, wherein non-unique identifiers are reused in multiple local networks of the plurality of local networks of the first and second tiles.

Interconnect network for multi-tile system on chips

An apparatus to facilitate a system-on-a-chip (SoC) architecture for low power state communication is disclosed. The apparatus includes a low power state fabric to provide a low power state path that avoids compute processing resources of the apparatus, and a low power state agent circuitry communicably coupled to the low power state fabric to update, in response to initiation of a low power state in the apparatus, a configuration of routers of the low power state fabric to utilize the low power state path provided by the low power state fabric, and to route memory transactions to the low power state path while the apparatus is in the low power state.

System-on-a-chip (SoC) architecture for low power state communication

In a further embodiment, a system on a chip integrated circuit (SoC) is provided that includes an active base die including a first cache memory, a first die mounted on and coupled with the active base die, and a second die mounted on the active base die and coupled with the active base die and the first die. The first die includes an interconnect fabric, an input/output interface, and an atomic operation handler. The second die includes an array of graphics processing elements and an interface to the first cache memory of the active base die. At least one of the graphics processing elements are configured to perform, via the atomic operation handler, an atomic operation to a memory device.

Atomic handling for disaggregated 3D structured SoCs

An infrastructure for a platform immersive experience is described. An example of an apparatus includes a microcontroller to receive control parameters for platform lighting options for a computing system and information regarding current system conditions for the computing system, and generate control instructions for a lighting pattern for a set of lights based at least in part on the control parameters and the information regarding current system conditions; and host control circuitry to receive the control instructions for the lighting pattern from the microcontroller, and provide control signals to control the set of lights.

Infrastructure for platform immersive experience

In one embodiment, a system on a chip integrated circuit (SoC) is provided that includes graphics processing resources including one or more graphics processing cores a memory subsystem including a memory controller, a physical interface, and a memory device and circuitry to dynamically adjust a voltage and frequency of the memory subsystem based on a workload executed by the graphics processing resources.

Dynamic voltage and frequency scaling for discrete graphics systems

Methods, apparatus, systems, and articles of manufacture are disclosed to reduce display connection latency. An example apparatus includes interface circuitry to: detect when a display is plugged into a port; and notify processor circuitry of the detection. In response to the notification, the processor circuitry of the example apparatus moves discrete circuitry into a high power state. The example apparatus also includes discrete circuitry to, while in the high power state, identify the display.

Methods and apparatus to reduce display connection latency

In one embodiment, an apparatus includes at least one fabric to interface with a plurality of intellectual property (IP) blocks of the apparatus, the at least one fabric including at least one status storage, and a fabric bridge controller coupled to the at least one fabric. The fabric bridge controller may be configured to initiate a functional safety test of the at least one fabric in response to a fabric test signal received during functional operation of the apparatus, receive a result of the functional safety test via the at least one status storage, and send to a destination location a test report based on the result. Other embodiments are described and claimed.

System, apparatus and method for functional testing of one or more fabrics of a processor

In one embodiment, an apparatus includes: an accelerator to execute instructions; an accelerator request decoder coupled to the accelerator to perform a first level decode of requests from the accelerator and direct the requests based on the first level decode, the accelerator request decoder including a memory map to identify a first address range associated with a local memory and a second address range associated with a system memory; and a non-coherent request router coupled to the accelerator request decoder to receive non-coherent requests from the accelerator request decoder and perform a second level decode of the non-coherent requests, the non-coherent request router to route first non-coherent requests to a sideband router of the first die and to direct second non-coherent requests to a computing die. Other embodiments are described and claimed.

System, apparatus and method for providing a fabric for an accelerator

In one embodiment, an apparatus includes multiple die and at least one interconnect to couple the die. A first die includes one or more cores, a first fabric and a first fabric transactor coupled to the first fabric, the first fabric transactor to initiate a functional test of the apparatus in response to a test signal, cause at least one first test transaction to be sent to a second die, receive a first response to the at least one first test transaction from the second die, and identify, based at least in part on the first response to the at least one test transaction, a location of a failure and report the location of the failure to a destination. Other embodiments are described and claimed.

System, apparatus and method for inter-die functional testing of an integrated circuit

In a computer system, a multilevel memory includes a near memory device and a far memory device, which are byte addressable. The multilevel memory includes a controller that receives a data request including original tag information. The controller includes routing hardware to selectively provide alternate tag information for the data request to cause a cache hit or a cache miss to selectively direct the request to the near memory device or to the far memory device, respectively. The controller can include selection circuitry to select between the original tag information and the alternate tag information to control where the data request is sent.

Dynamically programmable memory test traffic router

Embodiments of the present disclosure describe methods, apparatuses, storage media, and systems for in-field safety tests on system-level and circuit-level, providing real-time and on-chip tests with respect to, including but not limited to, circuit reliability, power consumption, and system safety. The in-field safety tests may include implementing voltage droop monitors (VDMs) and signature collectors with authentication-enabled launching. Other embodiments may be described and claimed.

Techniques in ensuring functional safety (fusa) systems

In one embodiment, an apparatus includes: at least one processing circuit; at least one array associated with the at least one processing circuit; a power controller to manage power consumption of the apparatus; and a fabric bridge coupled to the power controller. The fabric bridge and power controller may be configured to implement a handshaking protocol to enable the fabric bridge to receive data from the at least one array via a sideband communication path and send the data to a system memory coupled to the apparatus via a primary communication path, prior to entry of the apparatus into a first low power state. Other embodiments are described and claimed.

System, apparatus and method for handshaking protocol for low power state transitions

An apparatus is provided which comprises: a power management circuitry; and a processing circuitry comprising a processing core, wherein the power management circuitry is to: compute first voltage and frequency parameters, and transmit the first voltage and frequency parameters to the processing circuitry for operation of the processing core, and wherein in response to a detection of a fault, the power management circuitry is to: access second voltage and frequency parameters from a memory, and transmit the accessed second voltage and frequency parameters to the processing circuitry for operation of the processing core.

Redundancy in distribution of voltage-frequency scaling parameters

Growing community of inventors

Folsom, CA, United States of America

Lakshminarayana Pappu