International Business Machines Corporation

Lakshminarayana Baba Arimilli

Ravi Kumar Arimilli

William John Starke

Guy L Guthrie

James Stephen Fields, Jr

Ramakrishnan Rajamony

John Steven Dodson

Bernard Charles Drerup

Bartholomew Blaner

Jeffrey A Stuecheli

John David Irish

Sanjeev Ghai

William Evan Speight

Jerry Don Lewis

Leo James Clark

Hanhong Xue

Robert Sidney Blackmore

Jody B Joyner

Michael Steven Siegel

Richard Loise Arndt

Chulho Kim

Kenneth Michael Valk

Claude Basso

Balaram Sinharoy

Warren Edward Maule

Yiftach Benjamini

Derek E Williams

Jean Louis Calvignac

Etai Adar

Randal Craig Swanberg

Charles Francis Marino

Praveen S Reddy

Paul Frank Lecocq

Edward Joseph Seminaro

Bradly George Frey

Ronald Nick Kalla

David John Krolak

Curtis Carl Wollbrink

Gheorghe Calin Cascaval

James Steven Fields, Jr

Daniel Mark Dreps

Colin Beaton Verrilli

Michael Stephen Floyd

Hugh Shen

Christoph Raisch

Brian Mitchell Bass

Kevin Franklin Reick

Scott Michael Willenborg

Piyush Chaudhary

James Francis Mikos

David W Cummings

Larry Scott Leitner

Lonny Lambrecht

Jan-Bernd Themann

Jennifer Lane Vargus

In a data processing environment, a communication interface of a second host data processing system receives, from a first host data processing system, a host command in a first command set. The host command specifies a memory access to a memory coupled to the second host data processing system. The communication interface translates the host command into a command in a different second command set emulating coupling of an attached functional unit to the communication interface. The communication interface presents the second command to a host bus protocol interface of the second host data processing system. Based on receipt of the second command, the host bus protocol interface initiates, on a system fabric of the second host data processing system, a host bus protocol memory access request specifying the memory access.

Multifunction communication interface supporting memory sharing among data processing systems

An integrated circuit includes a first communication interface for communicatively coupling the integrated circuit with a coherent data processing system, a second communication interface for communicatively coupling the integrated circuit with an accelerator unit including an accelerator functional unit and an effective address-based accelerator cache for buffering copies of data from the system memory of the coherent data processing system, and a real address-based directory inclusive of contents of the accelerator cache. The real address-based directory assigns entries based on real addresses utilized to identify storage locations in the system memory. The integrated circuit includes request logic that, responsive to receipt on the first communication interface of a translation entry invalidation request, issues to the accelerator unit via the second communication interface an invalidation request that identifies an entry in the effective address-based accelerator cache to be invalidated utilizing a host tag identifying a storage location in the real address-based directory.

Translation invalidation in a translation cache serving an accelerator

An integrated circuit includes a first communication interface for communicatively coupling the integrated circuit with a coherent data processing system, a second communication interface for communicatively coupling the integrated circuit with an accelerator unit including an effective address-based accelerator cache for buffering copies of data from a system memory, and a real address-based directory inclusive of contents of the accelerator cache. The real address-based directory assigns entries based on real addresses utilized to identify storage locations in the system memory. The integrated circuit further includes request logic that communicates memory access requests and request responses with the accelerator unit. The request logic, responsive to receipt from the accelerator unit of a read-type request specifying an aliased second effective address of a target cache line, provides a request response including a host tag indicating that the accelerator unit has associated a different first effective address with the target cache line.

Integrated circuit and data processing system supporting address aliasing in an accelerator

An integrated circuit for a coherent data processing system includes a first communication interface for communicatively coupling the integrated circuit with the coherent data processing system, a second communication interface for communicatively coupling the integrated circuit with an accelerator unit including an effective address-based accelerator cache for buffering copies of data from a system memory of the coherent data processing system, and a real address-based directory inclusive of contents of the accelerator cache. The real address-based directory assigns entries based on real addresses utilized to identify storage locations in the system memory. The integrated circuit further includes request logic that communicates memory access requests and request responses with the accelerator unit via the second communication interface. A request response identifies a target of a corresponding memory access request utilizing a host tag specifying an entry associated with the target in the real address-based directory.

Integrated circuit and data processing system supporting attachment of a real address-agnostic accelerator

Hardware accelerator memory address translation fault resolution is provided. A hardware accelerator and a switchboard are in communication with a processing core. The hardware accelerator determines at least one memory address translation related to an operation having a fault. The operation and the fault memory address translation are flushed from the hardware accelerator including augmenting the operation with an entity identifier. The switchboard forwards the operation with the fault memory address translation and the entity identifier from the hardware accelerator to a second buffer. The operating system repairs the fault memory address translation. The operating system sends the operation to the processing core utilizing an effective address based on the entity identifier. The switchboard, supported by the processing core, forwards the operation with the repaired memory address translation to a first buffer and the hardware accelerator executes the operation with the repaired address.

Live partition mobility enabled hardware accelerator address translation fault resolution

An integrated circuit includes a first communication interface for communicatively coupling the integrated circuit with a coherent data processing system, a second communication interface for communicatively coupling the integrated circuit with an accelerator unit including an effective address-based accelerator cache for buffering copies of data from a system memory, and a real address-based directory inclusive of contents of the accelerator cache. The real address-based directory assigns entries based on real addresses utilized to identify storage locations in the system memory. The integrated circuit further includes directory control logic that configures at least a number of congruence classes utilized in the real address-based directory based on configuration parameters specified on behalf of or by the accelerator unit.

Integrated circuit and data processing system having a configurable cache directory for an accelerator

Hardware accelerator memory address translation fault resolution is provided. A hardware accelerator and a switchboard are in communication with a processing core. The hardware accelerator pulls an operation from a first buffer and adjusts a receive credit value in a first window context operatively coupled to the hypervisor. The receive credit value to limit a first quantity of one or more first tasks in the first buffer. The hardware accelerator determines at least one memory address translation related to the operation having a fault. The switchboard forwards the operation with the fault memory address translation from the hardware accelerator to a second buffer. The operation and the fault memory address translation are flushed from the hardware accelerator, and the operating system repairs the fault memory address translation. The switchboard forwards the operation with the repaired memory address translation from the second buffer to a first buffer and the hardware accelerator executes the operation with the repaired address.

Managed hardware accelerator address translation fault resolution utilizing a credit

Hardware accelerator memory address translation fault resolution is provided. A hardware accelerator and a switchboard are in communication with a processing core. The hardware accelerator determines at least one memory address translation related to an operation having a fault. The switchboard forwards the operation with the fault memory address translation from the hardware accelerator to a second buffer. The operation and the fault memory address translation are flushed from the hardware accelerator, and the operating system repairs the fault memory address translation. The switchboard forwards the operation with the repaired memory address translation from the second buffer to a first buffer and the hardware accelerator executes the operation with the repaired address.

Hardware accelerator address translation fault resolution

Managing lowest point of coherency (LPC) memory using a service layer adapter, the adapter coupled to a processor and an accelerator on a host computing system, the processor configured for symmetric multi-processing, including receiving, by the adapter, a memory access instruction from the accelerator; retrieving, by the adapter, a real address for the memory access instruction; determining, using base address registers on the adapter, that the real address targets the LPC memory, wherein the base address registers direct memory access requests between the LPC memory and other memory locations on the host computing system; and sending, by the adapter, the memory access instruction and the real address to a media controller for the LPC memory, wherein the media controller for the LPC memory is attached to the adapter via a memory interface.

Managing lowest point of coherency (LPC) memory using a service layer adapter

A processor core of a data processing system, in response to a first instruction, generates a copy-type request specifying a source real address and transmits it to a lower level cache. In response to a second instruction, the processor core generates a paste-type request specifying a destination real address associated with a memory-mapped device and transmits it to the lower level cache. In response to the copy-type request, the lower level cache copies a data granule from a storage location specified by the source real address into a non-architected buffer. In response to the paste-type request, the lower level cache writes the data granule from the non-architected buffer to the memory-mapped device. In response to receipt of the data granule, the memory-mapped device stores the data granule in a queue in the system memory associated with a hardware device of the data processing system.

Memory move instruction sequence targeting an accelerator switchboard

A memory lock mechanism within a multi-processor system is disclosed. A lock control section is initially assigned to a data block within a system memory of the multiprocessor system. In response to a request for accessing the data block by a processing unit within the multiprocessor system, a determination is made by a memory controller whether or not the lock control section of the data block has been set. If the lock control section of the data block has been set, the request for accessing the data block is denied. Otherwise, if the lock control section of the data block has not been set, the lock control section of the data block is set, and the request for accessing the data block is allowed.

Memory lock mechanism for a multiprocessor system

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Austin, TX, United States of America

Lakshminarayana Baba Arimilli