Intel Corporation

Lakshminarayan Krishnamurty

Tim Frodsham

David Stewart Dunning

Theodore Zale Schoenborn

Naveen Cherukuri

Sanjay Dabral

Aaron T Spink

Sanjay Darbal

A predetermined network packet is utilized for power reduction in either or both of a transmitter and receiver when information is not needed. Upon detection of the predetermined network packet type, various portions of the transmitter and/or receiver may be clock gated or powered down.

Method, apparatus, and system for idle state definition for power management

A loopback test to test a communication link for a layered interface where in a master agent programs the electrical parameters for the slave agent, such as, the offset, timing, and current compensation with a loopback control register. The slave agent's transmitter and receiver are independently controlled and the master agent may use a slave-echoed data test pattern to detect errors and subsequently sets the appropriate status bits in a loop back status register

Method, system, and apparatus for loopback parameter exchange

A testing procedure for distributed logic circuits that incorporates an efficient utilization of flip-flops to toggle detect for sensing output is discussed. The distributed logic circuit is a phase interpolator or a phase interpolator preceded by a DLL. The testing procedure utilizes enabling one of a plurality of independent programmable current sources and a flip-flop to toggle in response to the enabled current source to indicate a physical connection of the enabled distributed logic circuit current source.

Method and system for testing distributed logic circuitry

A loopback test to test a communication link for a layered interface where in a master agent programs the electrical parameters for the slave agent, such as, the offset, timing, and current compensation with a loopback control register. The slave and master agent to support an entry into the loopback test based on detection of a header within a packet. The slave and master agent to support exit out of the loopback test based on whether the loop count is finite.

Method, system, and apparatus for loopback entry and exit

A software self test engine is executed from a cache of a processor. The software self test engine is executed using an execution engine of the processor to perform a physical layer self test. The physical layer self test is performed by transmitting a test vector from the execution engine under control of the self test engine to an input/output ('I/O') unit of the processor along a datapath coupling the execution engine to the I/O unit. The test vector is transmitted along a loop back path including the I/O unit and the datapath to test a hardware device along the loop back path.

Cache based physical layer self test

A delay locked loop having short acquisition time to lock. The voltage controlled delay line includes a series of stages with the delay of each stage being variable. However, the initial stage has a fixed delay to avoid latching of the final stage to the first stage of the next cycle. The phase detector has additional logic gating to suppress an extraneous up or down signal during the acquisition time.

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Hillsboro, OR, United States of America

Lakshminarayan Krishnamurty