Qualcomm Incorporated

Lakshmikant Mamileti

Chiaming Chai

Stephen Edward Liles

Sanjay Bhikhubhai Patel

Clint Wayne Mumford

Anand Krishnamurthy

Dynamic voltage level shifting circuits, systems and methods are disclosed. A level shifting circuit comprises an input for accepting a first discrete voltage level to be shifted, a level shifting portion coupled to the input and to a second discrete voltage level, an enable portion having an enable input and coupled to the level shifting portion and an output. The level shifting circuit is configured to translate the data input at the first discrete voltage level into a second discrete voltage level. The enable portion is configured to selectively provide either the second discrete voltage level to the output or decouple at least a portion of the level shifting portion from the output based on the enable input.

Circuits, systems, and methods for dynamic voltage level shifting

Read and write data steering logic in the I/O of a memory array is tested by providing a data bus lane for each addressable subunit of a memory array storage location. Each bus lane is connected to the data input of a comparator. A BIST controller writes test patterns to the memory through the write steering logic and reads the test patterns in parallel to test the write steering logic. The BIST controller writes test patterns to the memory in parallel and reads the test patterns through the read steering logic to test the read steering logic. In both cases, a separate comparator dedicated to each bus lane verifies that the subunit data was properly shifted between the data bus lane and memory storage location subunit. The comparators are effectively disabled during normal operations to prevent logic gate switching.

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Cary, NC, United States of America

Lakshmikant Mamileti