Freescale Semiconductor,inc.

Lakshmi Narayan Ramanathan

Lakshminarayan Viswanathan

Jinbang Tang

Fernando A Santos

Audel Sanchez

Douglas G Mitchell

Tien Yu T Lee

Darrell Glenn Hill

Varughese Mathew

Trent Uehling

George R Leal

Philip H Bowles

Craig S Amrine

Scott K Pozder

Jianwen Xu

Jason R Fender

Neil T Tracht

Terry K Daly

Betty H Yeung

Jan Campbell

A packaged semiconductor device may include a termination surface having terminations configured as leadless interconnects to be surface mounted to a printed circuit board. A first flange has a first surface and a second surface. The first surface provides a first one of the terminations, and the second surface is opposite to the first surface. A second flange also has a first surface and a second surface, with the first surface providing a second one of the terminations, and the second surface is opposite to the first surface. A die is mounted to the second surface of the first flange with a material having a melting point in excess of 240&#xb0; C. An electrical interconnect extends between the die and the second surface of the second flange opposite the termination surface, such that the electrical interconnect, first flange and second flange are substantially housed within a body.

System, method and apparatus for leadless surface mounted semiconductor package

An electronic device can include an interconnect level including a bonding pad region. An insulating layer can overlie the interconnect level and include an opening over the bonding pad region. In one embodiment, a conductive stud can lie within the opening and can be substantially encapsulated. In another embodiment, the electronic device can include a barrier layer lying along a side and a bottom of the opening and a conductive stud lying within the opening. The conductive stud can substantially fill the opening. A majority of the conductive stud can lie within the opening. In still another embodiment, a process for forming an electronic device can include forming a conductive stud within the opening wherein from a top view, the conductive stud lies substantially completely within the opening. The process can also include forming a second barrier layer overlying the conductive stud.

Process of forming an electronic device including a conductive stud over a bonding pad region

A method () of packaging integrated circuit (IC) dies () includes applying () a laminating material () to a wafer (), and separating () the wafer () into multiple IC dies () such that the laminating material () is applied to back surfaces () of the IC dies (). Each of the IC dies () is positioned () with an active surface () facing a support substrate (). An encapsulant layer () is formed () overlying the laminating material () and the back surfaces () of the IC dies () from a molding compound (). The molding compound () and the laminating material () are removed from the back surfaces () of the IC dies () to form () openings () exposing the back surfaces (). Conductive material () is placed in the openings () and functions as a heat sink and/or a ground for the IC dies ().

Packaging an integrated circuit die with backside metallization

A method is disclosed for controlling warpage in an integrated electronic panel assembly including a plurality of die embedded within an encapsulant. The method comprises determining a number of build-up layers required for the integrated panel assembly. Each build-up layer contributes an amount of concavity to the integrated electronic panel assembly. A level of global convex warpage on the integrated panel assembly is then predicted, wherein the global convex warpage is provided by the presence of an embedded ground plane (EGP) alone within the integrated panel assembly and in the absence of any build-up layers. The embedded ground plane includes openings therein for accepting at least one die within a corresponding opening and it contributes a fixed amount of global convex warpage. An amount of local convex warpage to be introduced into the integrated electronic panel assembly is then determined, which together with the fixed amount of global convex warpage provides a combined convex warpage to the integrated electronic panel assembly. Accordingly, the global and local convex warpage counteract the concavity to be introduced subsequently by a build-up layer processing and is sufficient to enable subsequent planar processing of a completed integrated electronic panel assembly.

Method for controlling warpage in redistributed chip packaging panels

An electronic device can include an interconnect level () including a bonding pad region (). An insulating layer () can overlie the interconnect level () and include an opening () over the bonding pad region (). In one embodiment, a conductive stud () can lie within the opening () and can be substantially encapsulated. In another embodiment, the electronic device can include a barrier layer () lying along a side and a bottom of the opening () and a conductive stud () lying within the opening (). The conductive stud () can substantially fill the opening (). A majority of the conductive stud () can lie within the opening (). In still another embodiment, a process for forming an electronic device can include forming a conductive stud () within the opening () wherein the conductive stud () lies substantially completely within the opening (). The process can also include forming a second barrier layer () overlying the conductive stud ().

Electronic device including a conductive stud over a bonding pad region

A method is provided for forming a microelectronic assembly. A contact structure () is formed over a first side of a first substrate () having a microelectronic device formed over a second side thereof. The contact structure is electrically connected to the microelectronic device. A non-solderable layer () is formed over at least a portion of the contact structure and at least a portion of the first substrate. The contact structure and a second substrate () are interconnected with solder ().

Microelectronic assembly with back side metallization and method for forming the same

A process for removing metal from a scribe area of a semiconductor wafer. The metal removed may include exposed metal in a saw path of the scribe area and the metal in a crack stop trench of the scribe area. In one example, copper is removed from the scribe area by wet etching the wafer. In one example, the wet etching process is performed after the removal of an exposed barrier adhesion layer on the wafer surface. Removal of the metal in the saw path may reduce the amount of metal buildup on a saw blade during singulation of the die areas of a wafer.

Metal reduction in wafer scribe area

A passive integrated component ( ) is formed overlying a semiconductor substrate by etching a composite conductive layer using a solution of sodium persulfate or ceric ammonium nitrate to remove a lower portion of the composite copper layer ( ) exposed by an upper portion of the composite copper layer ( ) to expose an underlying surface ( ).

Growing community of inventors

Chandler, AZ, United States of America

Lakshmi Narayan Ramanathan