International Business Machines Corporation

Lakshmi Narasimha Reddy

Gi-Joon Nam

Sourav Saha

Christopher J Berry

Paul Gerard Villarrubia

Gustavo Enrique Tellez

Shyam Ramji

Stephen Thomas Quay

Ying Zhou

Louise Helen Trevillyan

Anthony DeGroff Drumm

Jiang Hu

Woohyun Chung

Zhuo Li

Charles Jay Alpert

Pinaki Chakrabarti

Arjen Alexander Mets

Cindy ShuiKing Washburn

Alexander Joel Suess

Matthew Mantell Ziegler

Thomas Edward Rosser

Benjamin Neil Trombley

Jagannathan Narasimhan

Michael Kazda

Chin Ngai Sze

Yaoguang Wei

Natarajan Viswanathan

Alexey Y Lvov

David Shing-Ki Kung

Myung-Chul Kim

Hua Xiang

Jarrod Alexander Roy

Jinwook Jung

Brian C Wilson

Kaustav Guha

Taraneh Taghavi

Nancy Y Zhou

Rongjian Liang

Diwesh Pandey

Michael H Wood

Prabhakar Nandavar Kudva

Adam P Matheny

Robert Alan Philhower

Robert Louis Franch

Wilm Ernst Donath

Leon Stok

Tuhin Mahmud

Andrew James Sullivan

Pooja M Kotecha

Frank Musante

Kanad Chakraborty

Glenn R Bee

Design rule violations ('DRVs') may be predicted using a design rule check (“DRC”) density map during a physical synthesis operation prior to executing a routing operation.

Rule check heatmap prediction

Embodiments are provided for enhanced initial global placement in a circuit design in a computing system by a processor. A wire length minimization may be determined based on maximum population density constraints as a single player game theory for global placement of an integrated circuit.

Enhanced alignment for global placement in a circuit

Techniques regarding parameter tuning for an EDA protocol are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise a tuning component that tunes an electronic design automation protocol via a cooperative co-evolutionary optimization framework that shares parameter knowledge across multiple stages of the electronic design automation protocol.

Multi-stage electronic design automation parameter tuning

To increase the efficiency of electronic design automation, at an end point of physical design synthesis optimization flow for a putative integrated circuit design having a plurality of nets, identify at least one congested region in the putative integrated circuit design. Identify those of the nets of the putative integrated circuit design traversing through the at least one congested region, to obtain a plurality of candidate nets for demotion. Demote a plurality of selected nets, selected from the plurality of candidate nets for demotion, from an upper routing layer of the putative integrated circuit design to a lower routing layer of the putative integrated circuit design. At least some of the plurality of selected nets experience a loss of timing quality of result after the demoting.

Routing layer re-optimization in physical synthesis

Embodiments for tuning parameters to a synthesis program are provided. At least one set of parameter settings for the synthesis program is selected. A plurality of identical synthesis jobs for the at least one set of parameter settings is run in an iteration of the synthesis program. Results of the iteration of the synthesis program are analyzed utilizing a tuning optimization cost function. Combinations of the parameter settings are created based on the analysis. At least one synthesis job for is run each of the combinations of the parameter settings in a subsequent iteration of the synthesis program. The analysis of the results, the creating of the combinations of parameter settings, and the running at the at least one synthesis job for each of the combinations of parameter settings are repeated until an exit criteria has been achieved.

Methods and systems for leveraging computer-aided design variability in synthesis tuning

Techniques that facilitate time-driven placement and/or cloning of components for an integrated circuit are provided. In one example, a system includes an analysis component, a geometric area component and a placement component. The analysis component computes timing information and distance information between a set of transistor components of an integrated circuit. The geometric area component determines at least a first geometric area of the integrated circuit and a second geometric area of the integrated circuit based on the timing information and the distance information. The placement component determines a location for a latch component on the integrated circuit based on an intersection between the first geometric area and the second geometric area.

Time-driven placement and/or cloning of components for an integrated circuit

A system and method to perform physical synthesis to transition a logic design to a physical layout of an integrated circuit include obtaining an initial netlist that indicates all components of the integrated circuit including memory elements and edges that interconnect the components. The method also includes generating a graph with at least one of the memory elements and the edges carrying one or more signals to the at least one of the memory elements or from the at least one of the memory elements. The components other than memory elements are not indicated individually on the graph. The netlist is updated based on the graph.

Memory element graph-based placement in integrated circuit design

For each of a plurality of source-sink pairs, a corresponding interconnect layer is selected having a reach length which permits propagation of a required signal within a required sink cycle delay. For a first clock cycle, a movable region for a first latch is located as a first plurality of overlapped regions one reach length from a source and the required sink cycle delay number of reach lengths from each one of the sinks; and the first plurality of overlapped regions is represented as nodes on a first cycle level of a topology search graph. Analogous actions are carried out for a second clock cycle of the required sink cycle delay. A latch tree is created based on the topology search graph, wherein a required number of latches is minimized, and at each of the cycle levels, all sinks of source nodes selected at a previous level are covered.

Multi-cycle latch tree synthesis

A computer-implemented method for optimizing microprocessor gates in a microprocessor includes receiving, via a processor, a dataset comprising a model of a plurality of gates of a microprocessor; determining, via the processor, whether a transmission line in the model, if implemented in a physical circuit, would result a signal transmission time less than a predetermined threshold time; applying to the model, via the processor, a proposed gate change to one or more of the plurality of gates; evaluating, via the processor and an area degradation based on the proposed gate change; determining, via the processor, a margin value based on the signal transmission time and an area degradation value; and making, via the processor, a gate change decision based on the margin value.

Dynamic microprocessor gate design tool for area/timing margin control

Optimizing timing in a VLSI circuit by generating a set of buffer solutions and determining a most critical delay and a sum of critical delays for each solution in the set of solutions. Quantifying a relationship between the most critical delay and the sum of critical delays for each solution. Comparing each solution's quantified relationship to the quantified relationship of each other solution in the set of solutions. Identifying, based on the comparing of each solution's relationship to the relationship of each other solution in the set of solutions, at least one solution in the set of solutions to have a worse relationship between the most critical delay and the sum of critical delays than the other solutions in the set of solutions. Pruning the at least one solution from the set of solutions.

Integrated circuit buffering solutions considering sink delays

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Briarcliff Manor, NY, United States of America

Lakshmi Narasimha Reddy