Apple Inc.

Telefonaktiebolaget Lm Ericsson (publ)

Lakshmi Narasimha Murthy Nukala

Gregory S Mathews

Shane J Keil

Sukalpa Biswas

Thejasvi Magudilu Vijayaraj

Kai Lun Hsiung

Yanzhe Liu

Rakesh L Notani

Thejasvi Magudilu Vijavaraj

Peter Fu

Sukulpa Biswas

Harshavardhan Kaushikkar

Tao Zhang

Techniques are disclosed relating to memory controllers and rate-limited traffic. In some embodiments, an apparatus includes memory controller circuitry configured to satisfy different quality-of-service parameters for multiple different classes of request traffic. The apparatus may also include multiple agents configured to send requests to the memory controller circuitry, where the agents operate according to a rate limit for a first class of traffic. The apparatus may include cache circuitry. In some embodiments, based on an allocation in the cache circuitry for a read operation of the first class that causes an eviction from the cache circuitry, the control circuitry is configured to perform a write operation of evicted data: as the first class of traffic and without counting the write operation toward the rate limit for the first class of traffic. In contrast, the control circuitry may count other write operations of the first class of traffic toward the rate limit.

Handling eviction write operations caused by rate-limited traffic

A memory control circuit coupled to multiple memory ranks may receive read and write requests for a different ranks of the multiple memory ranks. The memory control may allocate write requests to different slots based on the write requests target memory rank, and may adjust the number of slots available for a given memory rank during a write turn to improve write efficiency. The memory control circuit may also determine a number of ranks switches within a read turn based on whether a particular quality-of-service requirement associated with the read requests is being satisfied.

Read arbiter circuit with dual memory rank support

Systems, apparatuses, and methods for addressing bank hotspotting are described. A computing system includes a memory controller with an arbiter for determining how to arbitrate access to one or more memory device(s) for received requests. The arbiter categorizes each request in a manner that helps to ensure fair virtual channel distribution across the banks of the memory device(s). The category system includes bank hotspotting functions to give banks that have more requests more chances to go over banks with fewer requests. The category system is implemented proportionally with more category credits given to banks with higher bank depths within the virtual channel.

Memory bank hotspotting

Techniques are disclosed relating to multi-activation techniques for wire operations with multiple partial writes. In some embodiments, a memory controller is configured to access data in a memory device that supports partial writes having a first size using read-modify-write operations and non-partial writes having a second size that is greater than the first size. In some embodiments, the memory controller is configured to queue a first write operation having the second size, where the first write operation includes multiple partial writes. In some embodiments, the memory controller is configured to send separate activate signals to the memory device to activate a bank of the memory device to perform different proper subsets of the multiple partial writes. This may allow interleaving of other accesses to a memory bank and merging of writes while waiting for a current activation, in some embodiments.

Multi-activation techniques for partial write operations

An apparatus includes a memory circuit and a memory controller circuit. The memory controller circuit may include a write request queue. The memory controller circuit may be configured to receive a memory request to access the memory circuit and determine if the memory request includes a read request or a write request. A received read request may be scheduled for execution, while a received write request may be stored in the write request queue. The memory controller circuit may reorder scheduled memory requests based on achieving a specified memory access efficiency and based on a number of write requests stored in the write request queue.

Ordering memory requests based on access efficiency

Techniques relating to arbitration in a memory controller are disclosed. In some embodiments, the memory controller is configured to transition between read turns and writes turn according to a turn schedule. In some embodiments, the memory controller also receives reports from circuitry requesting memory transactions and determines a current latency tolerance value based on the reports. In some embodiments, the memory controller is configured to switch from a write turn to a read turn prior to a scheduled switch based on the current latency tolerance meeting a threshold value.

Write/read turn techniques based on latency tolerance

A memory controller circuit coupled to a memory circuit that includes multiple banks may receive multiple access requests including a particular access request to a particular bank of the plurality of banks. The particular access request is associated with a particular virtual channel of a plurality of virtual channels. The memory controller circuit may select a given access requests of the multiple access requests based on an arbitration category value associated with a virtual channel of the given access request and modify the arbitration category value in response to selecting the given access request.

Memory access scheduling using category arbitration

A method and apparatus for optimizing calibrations of a memory subsystem is disclosed. A memory controller of a memory subsystem includes a memory interface suitable for coupling to a DRAM having a plurality of banks. The memory controller includes a state machine the state machine may initiate calibration of circuitry within the memory controller. Responsive to initiating the calibration, the state machine also causes a refresh command to be transmitted to the DRAM. The calibration is then performed concurrent with the refresh of the DRAM. Subsequent to transmitting the refresh command, the state machine causes the memory interface to be placed into a low power state.

Method and apparatus for optimizing calibrations of a memory subsystem

A memory controller circuit coupled to multiple memory circuits may receive requests to access particular locations within the multiple memory circuits. A request may be assigned a particular quality-of-service level. During operation, the memory controller circuit may reallocate the quality-of-service level of a particular request to a new quality-of-service level based on accumulated bandwidth credits associated with the new quality-of-service level.

Memory access quality-of-service reallocation

A memory controller circuit coupled to multiple memory circuits may receive a read request for a particular one of the memory circuits and insert the read request into one of multiple linked lists that includes a linked list whose entries correspond to previously received read requests and are linked according to respective ages of the read requests. The memory controller circuit may schedule the read request using a head pointer of one of the multiple linked lists.

Memory access scheduling using a linked list

A memory request management system may include a memory device and a memory controller. The memory controller may include a read queue, a write queue, an arbitration circuit, a read credit allocation circuit, and a write credit allocation circuit. The read queue and write queue may store corresponding requests from request streams. The arbitration circuit may send requests from the read queue and write queue to the memory device based on locations of addresses indicated by the requests. The read credit allocation circuit may send an indication of an available read credit to a request stream in response to a read request from the request stream being sent from the read queue to the memory device. The write credit allocation circuit may send an indication of an available write credit to a request stream in response to a write request from the request stream being stored at the write queue.

Memory request management system

An embodiment of an apparatus includes a memory circuit and a memory controller circuit. The memory controller circuit may include a write request queue. The memory controller circuit may be configured to receive a memory request to access the memory circuit and determine if the memory request includes a read request or a write request. A received read request may be scheduled for execution, while a received write request may be stored in the write request queue. The memory controller circuit may reorder scheduled memory requests based on achieving a specified memory access efficiency and based on a number of write requests stored in the write request queue.

Techniques relating to arbitration in a memory controller are disclosed. In some embodiments, the memory controller implements a per-bank priority-based arbitration scheme for different types of memory traffic (e.g., with different quality of service parameters). In some embodiments, the memory controller is configured to provide per-bank overrides to the arbitration scheme based on latency tolerance reported by one or more requesters sending a particular type of memory traffic. Various techniques disclosed herein may improve performance, improve fairness among different types of memory traffic, and/or reduce power consumption.

Memory arbitration techniques based on latency tolerance

Methods and apparatus for minimizing resources for handling time-outs of read requests to a work queue in a work queue memory are described. According to one embodiment of the invention, a work queue execution engine receives a first read request when the work queue is configured in a blocking mode and is empty. A time-out timer is started in response to receiving the first read request. The work queue execution engine receives a second read request while the first read request is still pending, and the work queue is still empty. When the time-out timer expires for the first read request, the work queue execution engine sends an error response for the first read request and restarts the time-out timer for the second read request taking into account an amount of time the second read request has already been pending.

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Pleasanton, CA, United States of America

Lakshmi Narasimha Murthy Nukala