Agency for Science, Technology and Research

Other

Globalfoundries Singapore Pte. Ltd.

Institute of Microelectronics

Agency for Sceince, Technology and Reasearch

Lakshmi Kanta Bera

Sudhiranjan Tripathy

Surani Bin Dolmanan

Narayanan Balasubramanian

Shajan Mathew

Manippady Krishna Kumar

Rasanayagam Sivasayan Kajen

Eng Huat Toh

Hong Yu

Jae Gon Lee

Chung Foong Tan

Dim-Lee Kwong

Ranganathan Nagarajan

Chunshan Yin

Wei Yip Loh

Yee Chong Loke

Wai Hoe Tham

Balakumar Subramanian

Ming-Fu Li

Patrick Guo Oiang Lo

A method for fabrication of high electron mobility transistor (HEMT) semiconductor devices is presented. The method includes providing a substrate, growing a HEMT layer structure on the substrate; and self-aligned common metal stack formation of source, drain and gate electrodes on the HEMT layer structure using a single lithographic mask.

Self-aligning source, drain and gate process for III-V nitride MISHEMTs

There is provided a method for fabricating a semiconductor device having the following structure, and comprising the steps of growing a first and a second nucleation layer on a substrate; depositing a binary layer over these nucleation layers; and annealing the binary layer to form a first contact area and a second contact area on the substrate, wherein the annealed binary layer comprises a groupelement selected from Si, Ge and their combination thereof, and the annealed binary layer in the first and second contact areas are capable of providing a lower contact resistance for a current to flow in the device. This method serves to provide an intermediate layer which enables the fabrication process to become CMOS compatible.

Semiconductor device fabrication

There is provided a method for fabricating a semiconductor device having the following structure, and comprising the steps of growing a nucleation layer on a substrate; depositing a binary layer over the nucleation layer; and annealing the binary layer to form a first contact area and a second contact area on the substrate, wherein the annealed binary layer comprises a group 14 element selected from Si, Ge or their combination thereof, and the annealed binary layer in the first and second contact areas are capable of providing a lower contact resistance for a current to flow in the device. This method serves to provide an intermediate layer which enables the fabrication process to become CMOS compatible.

A method of manufacturing an integrated circuit system includes: providing a substrate having a channel region; forming a gate stack over a portion of the channel region with the gate stack having a floating gate for storing an electrical charge; forming a source recess in the substrate adjacent to the gate stack; and forming a source by layering a first bandgap material in the source recess.

Integrated circuit system with bandgap material and method of manufacture thereof

This invention relates to a semiconductor device making use of a highly thermal robust metal electrode as gate material. In particular, the development of Hafnium Nitride as a metal gate electrode (or a part of the metal gate stack) is taught and its manufacturing steps of fabrication with different embodiments are shown.

Thermal robust semiconductor device using HfN as metal gate electrode and the manufacturing process thereof

A process for forming both tensile and compressive strained silicon layers to accommodate channel regions of MOSFET or CMOS devices has been developed. After formation of shallow trench isolation structures as well as application of high temperature oxidation and activation procedures, the fabrication sequences used to obtain the strained silicon layers is initiated. A semiconductor alloy layer is deposited followed by an oxidation procedure used to segregate a germanium component from the overlying semiconductor alloy layer into an underlying single crystalline silicon body. The level of germanium segregated into the underlying single crystalline silicon body determines the level of strain, which is in tensile state of a subsequently selectively grown silicon layer. A second embodiment of this invention features the thinning of a portion of the semiconductor alloy layer prior to the oxidation procedure allowing a lower level of germanium to be segregated into a first underlying portion of the underlying single crystalline silicon body, while during the same oxidation procedure a second portion of the underlying single crystalline silicon body receives a higher level of germanium segregation. So the subsequently deposited silicon-germanium layer, although the same process and thickness, can be strained in different states (tensile or compressive) and levels, depending different underlying portions' germanium concentration.

Method of fabricating tensile strained layers and compressive strain layers for a CMOS device

A method of forming gate electrodes having different work functions includes forming a first well of a first conductivity type and a second well of a second conductivity type. Subsequently, a gate dielectric layer is deposited over the first and second wells. A multi-layer stack comprising two or more thin metal/metal nitride layers is next formed over the first well. A thick metal/metal nitride layer is formed over the multi-layer stack to form the first gate electrode. The thick metal/metal nitride layer is also formed over the gate dielectric layer portion extending over the second well, thereby forming the second gate electrode. The first and second electrodes are then annealed, and thereafter exhibit different work functions as desired.

Gate electrode architecture for improved work function tuning and method of manufacture

A process is described for trimming photoresist patterns during the fabrication of integrated circuits for semiconductor devices and MEMS devices. A combination of a low temperature (<20&deg; C.), high density oxygen and argon plasma and intense UV radiation is used to simultaneously trim and harden a photoresist linewidth in an ICP chamber. As an alternative, a UV hardening step can be performed in a flood exposure tool prior to the ICP plasma etch. Another option is to perform the argon plasma treatment first to harden the resist and then in a second step apply an oxygen plasma to trim the photoresist. Vertical and horizontal etch rates are decreased in a controllable manner which is useful for producing gate lengths in MOS transistors of less than 100 nm. The process can also be used to controllably increase a space width in a photoresist feature.

Low temperature resist trimming process

Growing community of inventors

Singapore, Singapore

Lakshmi Kanta Bera