Altera Corporation

Marvell International Limited

Xilinx, Inc.

Lakhbeer Singh Sidhu

Irfan Rahim

Jeffrey T Watt

John E Turner

Choy Hing Li

Michael J Hart

Srikanth Sundararajan

A method comprising applying a first voltage to a first transistor to create a defect in the first transistor, wherein (i) the first voltage is greater than a maximum operational voltage of the first transistor and (ii) the maximum operational voltage does not cause a defect in the first transistor when applied to the first transistor. The method further includes determining whether the first transistor has been programmed, including (i) measuring a first current through the first transistor, (ii) measuring a second current through a second transistor, and (iii) comparing the measured first current to the measured second current, wherein a difference between the measured first current and the measured second current indicates that the first transistor has been programmed.

Stress programming of transistors

An electronic fuse ('E-fuse') has a silicide filament link extending along a gap between polysilicon structures formed on a silicon substrate. The silicide filament link extends across diffusions formed in the gap. A P-N junction between terminals of the E-fuse provides high resistivity after programming (fusing) the silicide filament link.

E-fuse with scalable filament link

Methods for stressing transistors in order to program the transistors and for determining whether such transistors have indeed been programmed are described herein. The novel methods may include initially stressing a transistor by applying to the transistor a voltage greater than operational voltages of the transistor to create defects in the transistor. A current flowing through the transistor may then be measured to determine whether the transistor has been programmed, the measured current indicative of the presence of the defects.

A configuration memory cell ('CRAM') for a field programmable gate array ('FPGA') integrated circuit (&#x201c;IC&#x201d;) device is given increased resistance to single event upset (&#x201c;SEU&#x201d;). A portion of the gate structure of the input node of the CRAM is increased in size relative to the nominal size of the remainder of the gate structure. Part of the enlarged gate structure is located capacitively adjacent to an N-well region of the IC, and another part is located capacitively adjacent to a P-well region of the IC. This arrangement gives the input node increased capacitance to resist SEU, regardless of the logical level of the input node. The invention is also applicable to any node of any type of memory cell for which increased resistance to SEU is desired.

Integrated circuit structures for increasing resistance to single event upset

Methods and apparatus are provided for harnessing the effects of process variations in a semiconductor device. In one example, implementing an electronic design based on collected performance parameters is provided. In general, a core is segmented into multiple core regions. A performance parameter can be collected from each of the core regions. The performance parameter can be collected with a performance measuring mechanism associated with the core region. The performance parameter can be correlated to the performance requirements of an electronic device portion, and the electronic design portion can be implemented in a core region that has a performance parameter matched to the needs of the electronic design portion. In this way, process variation effects are harnessed by optimizing the implementation of the electronic design in regions of the semiconductor device best suited the needs of each electronic design portion. Therefore, performance/power optimization of the semiconductor device can be realized.

Performance/power mapping of a die

Programmable fuses for integrated circuits are provided. The fuses may be based on polysilicon or crystalline silicon fuse links coated with silicide or other conductive thin films. Fuses may be formed on silicon-on-insulator (SOI) substrates. A fuse may be blown by applying a programming current to the fuse link. The silicon or polysilicon in the fuses may be provided with a p-n junction. When a fuse is programmed, the silicide or other conductive film forms an open circuit. This forces current though the underlying p-n junction. Unlike conventional silicided polysilicon fuses, fuses with p-n junctions change their qualitative behavior when programmed. Unprogrammed fuses behave like resistors, while programmed fuses behave like diodes. The presence of the p-n junction allows sensing circuitry to determine in a highly accurate qualitative fashion whether a given fuse has been programmed.

Electrically-programmable integrated circuit fuses and sensing circuits

Integrated circuit inductors may be formed using a spiral layout on the surface of an interconnect dielectric stack. Conductive lines from two or more metal layers in the interconnect stack may be electrically connected using one or more via trenches. The via trench interconnection arrangement reduces the resistance of the inductor and increases the inductor's Q-factor. The Q-factor of the inductor may also be increased by placing a region of n-type and p-type wells or a metal plate region beneath the inductor to reduce power losses during operation. Shallow trench isolation may be used to reduce eddy currents and increase Q. The effects of copper dishing and trench blow-out may be used during inductor fabrication. A dual damascene fabrication process may be used.

Growing community of inventors

San Jose, CA, United States of America

Lakhbeer Singh Sidhu