Alcatel N.v.

Alcatel

Lajos Kiss

Joannes M Sevenhans

Peter P Reusens

Tim Gyselings

Paul Cautereels

Tim Vermeiren

François Pierre Constant Fredricx

Hans Maurice Felix Corneel Dequeker

Peter Vandaele

Patrick Albert Paul Renaux

Systems for transmitting information from terminal systems () via access multiplexers () comprising virtual forwarder systems () to networks are made less complex by inserting at the terminal systems () virtual forwarder internet protocol addresses () into destination fields of internet protocol headers for heading the information and by inserting destination internet protocol addresses () into routing fields of the internet protocol headers. Both the terminal systems () and the access multiplexers () should be made capable of dealing with internet protocol headers of the internet protocol version-4 or the internet protocol version-6 or higher, which comprise a destination field and a routing field. The destination internet protocol addresses () in the routing fields allow distinguishment between different classes of services and/or applications used by the terminal system () simultaneously, without the access multiplexers () being obliged to unpack (parts of) the information and to detect (parts of) the information at higher layers.

System comprising a terminal system, an access multiplexer and a network

A multi-sample multi-channel digital decimator filter producing a Finite Impulse filtering Response (FIR) from 128 digital filter coefficients for 4 independent channels with a decimation ratio of 32, i.e. each from 1,024 kHz 1-bit inputs to 32 kHz multibit outputs, splits cyclically the coefficient values in 16 groups of 8, according to the coefficient positions, into 4 Read Only Memory modules (0, 1, 2, 3). The Read Only Memory modules are coupled to the 4 multipliers (MULT 0, 1, 2, 3), wherein the coefficient value is multiplied by that of the input bit, through a multiplexer (MUXI) being able to cycle through 4 distinct conditions. The 4 adder accumulators (ACC 0, 1, 2, 3) are coupled to the outputs of their respective channel multipliers. They each partially compute in parallel outputs words using one sixteenth of the coefficients and the multiplexer rotates these words, thereby enabling complete computation in 4 cycles. 4 registers (REG 00, 01, 02, 03) are associated to each adder so as to compute 4 staggered output words simultaneously for each channel. A preferred filtering response can reduce the size of the Read Only Memory modules.

Digital filter and multi-channel decimator

A multiplex interpolator handles 4 series of multibit input words . . . , Si, Si+1, . . . applied in parallel at 32 kHz after conversion through an input series to parallel converter (SIPO) and produces 4 series of multibit output words at 256 kHz with the help of a parallel adder/subtractor (ADD) operated in multiplex to compute successively for each of the 4 series of input words, the output words 8Si, 7Si+Si+1, . . . , Si+7Si+1, 8Si+1, . . . , each addition of Si+1-Si being also computed by the adder/subtractor in two steps, first by subtracting (c1) Si from the accumulated (IVC) value and second, by adding (d1) Si+1 to the newly accumulated value, the adder/subtractor being initialized after each pair of steps prior to processing data pertaining to another of the 4 input words in a cyclic manner.

Interpolator increasing the output word rate of a digital signal

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Wilrijk, Belgium

Lajos Kiss