Siemens Aktiengesellschaft

Infineon Technologies Ag

Intel Corporation

Intel Deutschland Gmbh

Lajos Gazsi

Matthias Schoebinger

Xiaoning Nie

Stefan Meier

Andreas Wiesbauer

Stephan Henzler

Peter Gregorius

Peter Caldera

Jinan Lin

Dieter Bruckmann

Soenke Mehrgardt

Ferenc Leeb

Reinhard Stolle

Thomas Magesacher

Gonzalo Lucioni

Alois Rainer

Thomas Duda

J&ouml;rg Hauptmann

Walter Ulbrich

Matthias Schobinger

Jörg Bonhaus

Dieter Bruckman

Reiner Tonch

Embodiments relate to a frequency generator. The frequency generator comprises a quantization device configured to synthesize a carrier signal with a desired frequency characterized by a series of phase transitions at desired time instants, by approximating a phase transition at a desired time instant with a phase transition at a quantized effective time instant. The frequency generator further comprises a noise shaper configured to provide a noise-shaped feedback signal using the desired time instant and the effective time instant. Moreover, the frequency generator comprises an error generator configured to cause an error component within the effective time instant, the error component being at least 50 percent of a temporal quantization unit.

Frequency generator, method and computer program

A method for determining a sampling time of a signal, the method including: determining a candidate sampling time of a signal for input to a sampling circuit; determining a resultant sampling time at which the sampling circuit samples the signal when input with the candidate sampling time; and determining a sampling time of the signal based on a noise shaping of a difference between the resultant sampling time and the candidate sampling time.

Method for determining a sampling time of a signal, device for determining the same, and method for determining a sampling parameter of a signal

This application discusses, among other things, apparatus and methods for suppressing irrelevant edges of a phase modulated signal. In an example, a method can include receiving phase modulation information at a suppression circuit of a communication device, computing distances between transitions of a phase modulation signal, the phase modulation signal associated with the phase modulation information, comparing the distances to a threshold distance at a comparator of the suppression circuit, and suppressing a first transition of the phase modulation signal associated with the phase modulation information if a first distance is less than the threshold distance.

Removal of irrelevance in phase-modulated digital carrier-signals

Exemplary implementations of electrical circuits and systems are disclosed, and methods for signal processing including sampling and quantizing of amplitude and band limited signals implemented through a Passive Pulse Modulation Analog to Digital Converter (PMADC).

Data converter having a passive filter

This disclosure relates to analog to digital conversion using irregular sampling.

Analog to digital conversion using irregular sampling

A digital phase locked loop has a digitally controlled oscillator for generating an output frequency, a phase detector device for detecting the phase difference between a reference frequency and an output frequency of the oscillator. The phase detector device contains a delta-sigma frequency decision maker, and a digital loop filter, connected downstream of the phase detector device, for actuating the digitally controlled oscillator.

Digital phase locked loop for sub-&#x3bc; technologies

The present invention relates to a parallel multithread processor () with split contexts, with M parallel-connected standard processor root units () being provided for instruction execution of program instructions for different threads (T), and with N context memories () being provided, which each temporarily store a current state of a thread (T), and with a thread monitoring unit () being provided, by means of which each standard processor root unit () can be connected to each context memory (). The invention accordingly provides a processor architecture in which a number N of different context memories () and corresponding threads (T) are effectively fully networked with a number M of standard processor root units (). This means that use is made not only of paralleling of the standard processor root units (), but also of the threads (T) and of the context memories ().

Parallel multithread processor (PMT) with split contexts

A device for the production of standard compliant signals, for example pulse-type signals in a telecommunication network, serves the production and adaptation and/or pre-distortion of signals with a certain signal form, which is defined dependent on a standard signal form specified in a standard. The device comprises signal generation means () for the production of the signals with a certain signal form and signal adjustment means () for the adaptation or pre-distortion of the signals. The signal generation means () according to the invention are digitally realized, by using a programmable shift register (), which contains multipliers specified by the standard signal form for multiplication with a digital input signal (). The signal adjustment means () comprise substantially scalable digital filter arrangements in the form of a serial connection of digital filters () with a downstream multiplexer (). Moreover, the invention provides attenuating means () for attenuation of the signal dependent on the characteristics of the telecommunication channel.

Device for the production of standard-compliant signals

The invention relates to a device for correcting a receiver signal which is associated with an emission signal transmitted in a distorted transmission system. The emission signal comprises periods which can be determined by analyzing the received signal wherein determined properties are exhibited which are suitable for adjusting the correction. According to one embodiment, the device comprises a component for adjusting the correction based upon an analysis of the received signal and a component for monitoring and enabling the adjusting component when the received signal associated with the transmission signal exhibits certain characteristics.

Device for correcting a receiving signal

The invention relates to a heterogeneous parallel multithread processor () with shared contexts which has a plurality (M) of parallel-connected standard processor root unit types (; p&#x2208; [1, . . . , M]), where each respective standard processor root unit type () has at least one or more (K) parallel-connected standard processor root units (; q&#x2208; [1, . . . , K]) for instruction execution of program instructions from various threads (T), each standard processor root unit type () having N local context memories () which each buffer-store part of a current processor state for a thread. The multithread processor () also has a plurality (N) of global context memories (; t&#x2208; [1, . . . , N]) which each buffer-store part of a current processor state for a thread, and a thread control unit () which can connect any standard processor root unit () to any global context memory ().

Heterogeneous parallel multithread processor (HPMT) with local context memory sets for respective processor type groups and global context memory

To reconstruct data transmitted over a transmission path, for example a cable, the corresponding signal received by the receiver is firstly amplified and subsequently made discrete by means of an A/D-converter (), in order to obtain a suitable digital signal, whereby the signal amplified for this purpose is scanned with a relatively low sampling rate, which can frequently lie in the Nyquist range or can be even less than the Nyquist frequency. Subsequently the signal made discrete in this way is filtered by means of a digital high pass filter () and equalized by means of a digital cable approximation filter () to compensate any distortion occurring during the transmission over the transmission path. By means of a phase locked loop () a regenerated clock (CLK) and synchronous with this clock the originally transmitted data (DATA) is recovered from the digital signal processed in this way.

Method of reconstructing data transmitted over a transmission path in a receiver and corresponding device

High-speed router for transmitting data packets, containing header data and useful data, between data networks, the router including a plurality of data processing processors for parallel data processing of the header data, a demultiplexer for separating the data packets into header data and useful data, and a distribution processor for distributing the separated header data among the data processing processors. The distribution processor distributes the header data at least in part on the basis of a priority specified by the header data and the workload of the data processing processors.

High-speed router

Interpolation filter circuit for a digital communication device for the filtering and clock-rate conversion of a digital input signal received from a data source with a symbol-clock data rate, having

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Düsseldorf, Germany

Lajos Gazsi