Ubilite, Inc.

Qualcomm Incorporated

Lai Xu

Matthew Levi Severson

Ronald Alton

Jeffrey Gemar

Vijayakumar Ashok Dibbad

Mahadevamurty Nemani

Gabriel A Watkins

Power limiting in a processor-based system based on allocating power budgets for different sub-systems based on multiple time-based power limits is disclosed. The processor-based system has multiple power consuming sub-systems (e.g., non-processing unit (PU) and PU sub-systems) that demand and consume power from a power source of the processor-based system. To limit overall power consumption of the processor-based system over different time-based power limits, the processor-based system includes a power limiter circuit. The power limiter circuit is configured to manage multiple, different time-based (e.g., time constant) power limits for the processor-based system and to allocate corresponding power limit budgets to constrain power consumption of different sub-systems based on the multiple time-based power limits. The power limiter circuit can be configured to constrain power consumption of a PU sub-system to a total PU sub-system power limit budget based on the multiple time-based power limits.

Power limiting in a processor-based system based on allocating power budgets for different sub-systems based on multiple time-based power limits

A radio module, comprises a battery; and a radio circuit, the radio circuit comprising: a DC-to-DC converter coupled with the batters and configured to convert a battery voltage to a first DC voltage level; at least one regulator coupled with the DC-to-DC converter and configured to covert the first DC voltage level to a second DC voltage level; at least one circuit block coupled with the at least one regulator such that the second DC voltage level is configured to provide power to the at least one circuit block; a real time clock configured to provide a clock signal to the at least one circuit block; and a management unit coupled with the at least one circuit block and configured to implement a state machine to control the at least one circuit block, wherein the state machine causes the management unit to cause the second DC voltage level to be removed from the at least one circuit during a first state comprising the state machine and, during a second state comprising the state machine, cause the second DC voltage level to be provided to the at least one circuit block, cause certain components within the circuit block to be reset, and provide a start signal to the circuit block enabling the circuit block to perform a function, and wherein the circuit block is configured to generate a signal indicating the function has been completed that is provided to the management unit, which causes the state machine to transition to a third state in which the second DC voltage is gain removed from the at least one circuit block.

Systems and methods for power management in low power communication device and system

A radio module, radio module, comprising a battery; and a radio circuit, the radio circuit comprising: a DC-to-DC converter coupled with the batters and configured to convert a battery voltage to a first DC voltage level; at least one regulator coupled with the DC-to-DC converter and configured to covert the first DC voltage level to a second DC voltage level; a plurality of circuit blocks coupled with the at least one regulator such that the second DC voltage level is configured to provide power to the plurality of circuit blocks; a real time clock configured to provide a clock signal to the plurality of circuit blocks; and a management unit coupled with the plurality of circuit blocks and configured to implement a state machine to control the plurality of circuit blocks, wherein the state machine causes the management unit to cause the second DC voltage level to be applied to and removed from at least some of the plurality of circuit blocks during various states comprising the state machine, wherein the plurality of circuit blocks comprise a real time clock and a retention memory configured to store register values and component values for the plurality of circuit blocks, and wherein the management unit comprises a wake up logic circuit, the state machine comprising a lower power state in which only the wake up logic circuit, real time clock, and retention memory are on.

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San Diego, CA, United States of America

Lai Xu