Taiwan Semiconductor Manufacturing Comp. Ltd.

Lai-Wan Chong

Kei-Wei Chen

Chun Hsiung Tsai

Chien-Wei Lee

Tsan-Chun Wang

Wen-Chu Hsiao

Ying-Min Chou

Hsiang-Hsiang Ko

Chien-wei Lee

Present disclosure provides a FinFET structure, including a substrate, a fin protruding from the substrate, including a first portion and a second portion below the first portion, wherein the first portion includes a first dopant concentration of a dopant, and the second portion includes a second dopant concentration of the dopant, the second dopant concentration is greater than the first dopant concentration, a gate over the fin, wherein the second portion of the fin is below a bottom surface of the gate, and an insulating layer over the substrate and proximal to the second portion of the fin, wherein at least a first portion of the insulating layer includes a third dopant concentration of the dopant, the third dopant concentration is greater than the first dopant concentration.

FinFET structure and method for manufacturing thereof

Present disclosure provides a FinFET structure, including a fin and a gate surrounding a first portion of the fin. A dopant concentration in the first portion of the fin is lower than about 1E17/cm. The FinFET structure further includes an insulating layer surrounding a second portion of the fin. The dopant concentration of the second portion of the fin is greater than about 8E15/cm. The insulating layer includes a lower layer and an upper layer, and the lower layer is disposed over a substrate connecting to the fin and has a dopant concentration greater than about 1E19/cm.

A method of fabricating a semiconductor device. The method includes forming source/drain features in a substrate on opposite sides of a gate structure, forming an etch stop layer over the source/drain features, and depositing a dielectric layer on the etch stop layer. The method further includes performing a first atomic layer etching (ALE) process having a first operating parameter value on the dielectric layer to form a first part of an opening, and performing a second ALE process having a second operating parameter value to extend the opening to expose the source/drain features. The first operating parameter value is different from the second operating parameter value.

Semiconductor device and fabrication method therefor

A semiconductor structure that includes crystalline surfaces and amorphous hydrophilic surfaces is provided. The hydrophilic surfaces are treated with silane that includes a hydrophobic functional group, converting the hydrophilic surfaces to hydrophobic surfaces. Chemical vapor deposition or other suitable deposition methods are used to simultaneously deposit a material on both surfaces and due to the surface treatment, the deposited material exhibits superior adherence qualities on both surfaces. In one embodiment, the structure is an opening formed in a semiconductor substrate and bounded by at least one portion of a crystalline silicon surface and at least one portion of an amorphous silicon oxide structure.

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Kaohsiung, Taiwan

Lai-Wan Chong