Qualcomm Incorporated

Lai Kan Leung

Chiewcharn Narathong

Chirag Dipak Patel

Aleksandar Miodrag Tasic

Rajagopalan Rangarajan

Timothy Donald Gathman

Dongling Pan

Yiwu Tang

Xinmin Yu

Jong Min Park

Dongmin Park

Kyle David Holland

Ojas Choksi

Ravi Sridhara

Janakiram Ganesh Sankaranarayanan

Jang Joon Lee

Jun Tan

Chih-Fan Liao

Mehmet Ipek

Gurkanwal Singh Sahota

Bhushan Shanti Asuri

Shrenik Patel

Jingcheng Zhuang

Christian Holenstein

Yunfei Feng

Soon-Seng Lau

Tomas O'Sullivan

Jianjun Yu

Jian Kang

Tingfang Ji

Joseph Binamira Soriaga

Krishna Kiran Mukkavilli

Muhammad Sayed Khairy Abdelghaffar

Raghu Narayan Challa

Joseph Patrick Burke

Jeremy Darren Dunworth

Li Liu

Allen Minh-Triet Tran

Gary John Ballantyne

Dinesh Jagannath Alladi

Chinmaya Mishra

Francesco Gatta

Zhang Jin

Kevin Hsi Huai Wang

Elias Dagher

Kevin Hsi-Huai Wang

Yue Chao

Yuhua Guo

Ketan Humnabadkar

Jianyun Hu

Devavrata Vasant Godbole

Youngchang Yoon

Charline Hao

Praveen-Kumar Sampath

Praveen Sampath

Yingying Li

Rahul Kodkani

An amplifying circuit includes a first reconfigurable amplifier configured to selectively operate in a cascode mode or a non-cascode mode, wherein an input of the first reconfigurable amplifier is coupled to a first input of the amplifying circuit, and an output of the first reconfigurable amplifier is coupled to an output of the amplifying circuit. The amplifying circuit also includes a second reconfigurable amplifier configured to selectively operate in the cascode mode or the non-cascode mode, wherein an input of the second reconfigurable amplifier is coupled to a second input of the amplifying circuit, and an output of the second reconfigurable amplifier is coupled to the output of the amplifying circuit.

Reconfigurable amplifier

An amplifier may include multiple stages, with the multiple stages arranged in a fan-out configuration. The fan-out configuration provides multiple amplified signals at multiple amplifier output nodes, which may be coupled to a shared set of downconverters. The shared downconverters may support processing of only a smaller bandwidth than the largest possible bandwidth of an input RF signal input to the amplifier. For example, the downconverters may support a bandwidth matching a smallest bandwidth of a supported RF signal. For example, when the amplifier is intended to support 5G mmWave RF signals and 5G sub-6 GHz RF signals, the downconverters may each individually support a bandwidth of carriers in the 5G sub-6 GHz RF signals but not individually support the entire bandwidth of a possible 5G mmWave RF signal.

Fan-out multi-stage amplifier with configurable paths

Methods and apparatus for storing a control voltage of a phased-locked loop (PLL) when switching from mission mode to standby mode for the PLL, and for restoring the control voltage of the PLL when switching back to mission mode. An example PLL circuit includes a charge pump, a voltage-controlled oscillator (VCO) having a control input coupled to an output of the charge pump via a node, and a tracking circuit coupled to the node. The tracking circuit is generally configured to sample a voltage of the node during a mission mode, save a representation of the sampled voltage before entering a standby mode, and restore the sampled voltage to the node for reentering the mission mode using the saved representation of the sampled voltage.

Tuning voltage tracker for receive/transmit phase-locked loop (PLL) fast switching

During an uplink TDD slot, an UL UE transmits an UL signal that occupies a slot frequency range. Similarly, during a DL TDD slot, a DL UE receives a DL signal that occupies the slot frequency range. But during an SBFD slot, a UL UE transmits a UL signal that occupies only a first sub-band of the slot frequency range. Similarly, a DL UE receives a DL signal during an SBFD slot that occupies only a second sub-band of the slot frequency range. The second sub-band is distinct from the first sub-band. The DL UE may thus mitigate UE-to-UE interference during an SBFD slot by filtering the DL signal to substantially block the second sub-band from being received at the DL UE.

Sub-band-full-duplex interference mitigation

Embodiments of this disclosure may include a receiver with a reconfigurable processing path for different signal conditions. Such a receiver may reconfigure between a mixer-first configuration and an amplifier-first configuration. In the mixer-first configuration, an RF input signal is not passed through an LNA for amplification before processing the RF input signal for downconversion to baseband and eventual extraction of the information in the signal. In the amplifier-first configuration, an RF input signal is passed through an LNA for amplification before processing the RF input signal for downconversion to baseband and eventual extraction of the information in the signal. Reconfiguring the receiver between mixer-first and amplifier-first configurations may be performed based on detection of jammer signals and/or measurement of signal-to-noise ratio (SNR).

Configurable receive path for mixer-first or amplifier-first signal processing

A reconfigurable amplifier includes a first transistor having a gate coupled to an input of the reconfigurable amplifier, and a source coupled to a ground. The reconfigurable amplifier also includes a gate control circuit, and a second transistor having a gate coupled to the gate control circuit, a source coupled to a drain of the first transistor, and a drain coupled to an output of the reconfigurable amplifier, wherein the gate control circuit is configured to output a bias voltage to the gate of the second transistor in a cascode mode, and output a switch voltage to the gate of the second transistor in a non-cascode mode. The reconfigurable amplifier further includes a load coupled to the output of the reconfigurable amplifier.

The disclosure relates to an apparatus including a receiver configured to process a radio frequency (RF) signal to generate a baseband signal; a radio frequency (RF) jammer detector configured to generate a signal indicative of whether an RF jammer is present at an input of the receiver; and a receiver bias circuit configured to generate a supply voltage for the receiver based on the RF jammer indication signal. In another aspect, the apparatus includes constant gain bias circuit to maintain the gain of the receiver constant in response to changes in the supply voltage. In other aspects, the receiver bias circuit may suspend the generating of the supply voltage based on the RF jammer indication signal if the power level of the target received signal is above a threshold. In other aspects, the receiver bias circuit changes the supply voltage during cyclic prefix (CP) intervals between downlink intervals.

Biasing technique for receiver based on radio frequency (RF) jammer detection

An example apparatus includes a polyphase transconductance-capacitor filter. The polyphase filter includes a DC bias voltage node, a plus in-phase filter unit, a minus in-phase filter unit, a plus quadrature-phase filter unit, and a minus quadrature-phase filter unit. Each filter unit respectively includes an input node, an output node, and a control node. The polyphase filter also includes a plus in-phase switch and a minus in-phase switch. The plus in-phase switch is coupled to the control node of the plus in-phase filter unit, the DC bias voltage node, and the input node of one or both of the plus quadrature-phase filter unit and the minus quadrature-phase filter unit. The minus in-phase switch is coupled to the control node of the minus in-phase filter unit, the DC bias voltage node, and the input node of one or both of the plus quadrature-phase filter unit and the minus quadrature-phase filter unit.

Polyphase filter with interphase coupling

An apparatus is disclosed for bidirectional amplification with phase-shifting. In example implementations, an apparatus includes a phase shifter with a bidirectional amplifier. The bidirectional amplifier includes a first transistor coupled between a first plus node and a second minus node, a second transistor coupled between a first minus node and a second plus node, a third transistor coupled between the first plus node and the second minus node, and a fourth transistor coupled between the first minus node and the second plus node. The bidirectional amplifier also includes a fifth transistor coupled between the first plus node and the second plus node, a sixth transistor coupled between the first minus node and the second minus node, a seventh transistor coupled between the first plus node and the second plus node, and an eighth transistor coupled between the first minus node and the second minus node.

Phase shifter with bidirectional amplification

An apparatus is disclosed for phase-shifting signals. In example implementations, the apparatus includes a phase shifter. The phase shifter includes a first port, a second port, a vector modulator coupled to the first port, and a signal phase generator. The signal phase generator includes multiple amplifiers coupled between the vector modulator and the second port. The signal phase generator also includes multiple capacitors that couple the multiple amplifiers together to form a loop. Each respective capacitor of the multiple capacitors is coupled between a respective pair of consecutive amplifiers of the multiple amplifiers to form the loop.

Phase shifter with active signal phase generation

Wireless signal processing may be improved by using a configurable baseband filter (BBF) in the receive path of a transceiver. A configurable BBF may accommodate processing of different wireless signals in a single integrated circuit (IC) chip. For example, a single IC may support processing of 5G mmWave RF signals and 5G sub-7 GHz RF signals by reconfiguring the BBF with settings appropriate for the different wireless signals. The reconfiguring of the BBF may include adjusting a bandwidth of the BBF and/or adjusting a filter order of the BBF. The reconfiguring of the BBF may be performed in response to detection of jammer signals to improve rejection of the jammer signals.

Reconfigurable baseband filter

An apparatus is disclosed for bidirectional variable gain amplification. In an example aspect, an apparatus comprises an antenna element of an antenna array and a wireless transceiver. The wireless transceiver comprises a transmit path coupled to the antenna element, a receive path coupled to the antenna element, and a phase shifter disposed in both the transmit path and the receive path. The phase shifter is configured to operate in an active mode and comprises a first bidirectional variable gain amplifier and a second bidirectional variable gain amplifier.

Bidirectional variable gain amplification

Certain aspects of the present disclosure provide methods and apparatus for processing signals using a current-mode biquad filter, which may have a tunable bias current and/or tunable capacitance. One example apparatus is a current-mode biquad filter circuit that includes a first input current node, a first capacitive element coupled to the first input current node, a first output current node, a first active filter circuit coupled between the first input current node and the first output current node, and a second active filter circuit coupled between the first input current node and the first output current node. The second active filter circuit is complementary to the first active filter circuit.

Complementary current-mode biquad with high linearity

In certain aspects, a receiver includes first amplifiers, wherein each one of the first amplifiers comprises an input and an output. The receiver also includes second amplifiers, wherein each one of the second amplifiers comprises an input and an output, and the outputs of the second amplifiers are coupled to a combining node. The receiver also includes transmission lines, wherein each one of the transmission lines is coupled between the output of a respective one of the first amplifiers and the input of a respective one of the second amplifiers. The receiver further includes a load coupled to the combining node, and receiver elements, wherein each one of the receiver elements comprises an input and an output, and the output of each one of the receiver elements is coupled to the input of a respective one of the first amplifiers.

Signal combiner

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San Marcos, CA, United States of America

Lai Kan Leung