Texas Instruments Corporation

Lahir Shaik Adam

Mahalingam Nandakumar

Alwin J Tsao

Eddie Hearl Breashears

Amitabh Jain

Manoj Mehrotra

Song Zhao

Formation of an NMOS transistor is disclosed, where at least one of carbon, atomic fluorine and molecular fluorine (F) are combined with implantations of at least one of arsenic, phosphorous and antimony. The dopant combinations can be used in LDD implantations to form source/drain extension regions, as well as in implantations to form halo regions and/or source/drain regions. The combinations of dopants help to reduce sheet resistance and increase carrier mobility, which in turn facilitates device scaling and desired device performance.

Implantation of carbon and/or fluorine in NMOS fabrication

The present invention provides a tri-gate lower power device and method for fabricating that tri-gate semiconductor device. The tri-gate device includes a first gate [] located over a high voltage gate dielectric [] within a high voltage region [], a second gate [] located over a low voltage gate dielectric [] within a low voltage core region [] and a third gate [] located over an intermediate core oxide [] within an intermediate core region []. One method of fabrication includes forming a high voltage gate dielectric layer [] over a semiconductor substrate [], implanting a low dose of nitrogen [] into the semiconductor substrate [] in a low voltage core region [], and forming a core gate dielectric layer [] over the low voltage core region [], including forming an intermediate core gate dielectric layer [] over an intermediate core region [

Tri-gate low power device and method for manufacturing the same

The present invention facilitates semiconductor fabrication by providing methods of fabrication that apply tensile strain to channel regions of devices while mitigating unwanted dopant diffusion, which degrades device performance. Source/drain regions are formed in active regions of a PMOS region (). A first thermal process is performed that activates the formed source/drain regions and drives in implanted dopants (). Subsequently, source/drain regions are formed in active regions of an NMOS region (). Then, a capped poly layer is formed over the device (). A second thermal process is performed () that causes the capped poly layer to induce strain into the channel regions of devices. Because of the first thermal process, unwanted dopant diffusion, particularly unwanted p-type dopant diffusion, during the second thermal process is mitigated.

Method to strain NMOS devices while mitigating dopant diffusion for PMOS using a capped poly layer

The present invention provides a tri-gate lower power device and method for fabricating that tri-gate semiconductor device. The tri-gate device includes a first gate [located over a high voltage gate dielectric [within a high voltage region [, a second gate [located over a low voltage gate dielectric [within a low voltage core region [and a third gate [located over an intermediate core oxide [within an intermediate core region [. One method of fabrication includes forming a high voltage gate dielectric layer [over a semiconductor substrate [, implanting a low dose of nitrogen [] into the semiconductor substrate [in a low voltage core region [, and forming a core gate dielectric layer [over the low voltage core region [, including forming an intermediate core gate dielectric layer [over an intermediate core region [

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Plano, TX, United States of America

Lahir Shaik Adam