International Business Machines Corporation

Globalfoundries Inc.

Other

Stmicroelectronics Gmbh

Globalfoundries U.S. Inc.

Applied Materials, Inc.

Globalfoundries Singapore Pte. Ltd.

Novellus Systems Incorporated

Infineon Technologies North America Corp.

Laertis Economikos

Ruilong Xie

Hui Zang

Chanro Park

Haiting Wang

Jiehui Shu

Shesh Mani Pandey

John H Zhang

Byeongju Park

Richard Anthony Conti

Jinping Liu

Eric D Perfecto

Mario John Interrante

Chandrika Prasad

Alexander William Simpson

Garo Jacques Derderian

Hariklia Deligianni

Andrew Mark Greene

Roy Rongqing Yu

Ravikumar Ramachandran

Hong Yu

John Anthony Fitzsimmons

Raschid Jose Bezama

Haigou Huang

James L Speidell

Robert Hannon

Guowei Xu

Lawrence Alfred Clevenger

Jeffrey P Gambino

Jack Allan Mandelman

Veeraraghavan S Basker

David Clifford Long

Min Gyu Sung

Kevin Shawn Petrarca

John Michael Cotte

Xusheng Kevin Wu

Rajarao Jammy

Chandrasekhar Narayan

Wesley Charles Natzle

David Edward Kotecki

Mark J LaPlante

David M Dobuzinsky

George D Papasouliotis

Lester W Herron

Lei Sun

Ashima B Chakravarti

Rajesh S Patel

Kangguo Cheng

Effendi Leobandung

Carl John Radens

Theodorus E Standaert

Ramachandra Divakaruni

Mukta G Farooq

Lars W Liebmann

Herbert Lei Ho

Xunyuan Zhang

Daniel Chanemougame

Richard Paul Volant

Guillaume Bouche

Thomas W Dyer

John Ryan Sporre

Bomy A Chen

Tze-Chiang Chen

Gary Bela Bronner

Rajasekhar Venigalla

Min Yang

Hussein Ibrahim Hanafi

Ruchir Puri

Dae-Gyu Park

Jochen C Beintner

John Leonard Sudijono

Johnathan E Faltermeier

Roger Allan Quon

Stephen Edward Greco

Byeong Yeol Kim

Michael P Belyansky

Thomas Anthony Wassick

Patrick A Van Cleemput

Rama Divakaruni

Panayotis Constantinou Andricacos

Mahmoud M Khojasteh

Hiroyuki Akatsu

Kenneth Jay Stein

Scott David Halle

William J Cote

Guoxiang Ning

Daniel J Jaeger

Ian D Melville

Xiaoyan Shao

Scott Beasor

Thomas Safron Kanarsky

Jerome Ciavatti

Michael F McAllister

Madhavan Swaminathan

Gopalakrishna B Prabhu

Jingyu Lian

Hsien-Ching Lo

Gerhard Kunkel

Rajeev Malik

Young-Hee Kim

A semiconductor device includes one or more fins extending from a substrate, the one or more fins having source/drain epitaxial grown material (S/D epitaxy) thereon that merges one or more fins, a gate formed over the one or more fins, the gate including high k metal gate disposed between gate spacers and a metal liner over the S/D epitaxy and sides of the gate spacers. The gate includes a self-aligned contact cap over the HKMG and the metal liner.

Formation of trench silicide source or drain contacts without gate damage

A transistor device disclosed herein includes, among other things, a gate electrode positioned above a semiconductor material region, a sidewall spacer positioned adjacent the gate electrode, a gate insulation layer having a first portion positioned between the gate electrode and the semiconductor material region and a second portion positioned between a lower portion of the sidewall spacer and the gate electrode along a portion of a sidewall of the gate electrode, an air gap cavity located between the sidewall spacer and the gate electrode and above the second portion of the gate insulation layer, and a gate cap layer positioned above the gate electrode, wherein the gate cap layer seals an upper end of the air gap cavity so as to define an air gap positioned adjacent the gate electrode.

Transistor comprising an air gap positioned adjacent a gate electrode

At least one method, apparatus and system disclosed herein involves adjusting for a misalignment of a gate cut region with respect to semiconductor processing. A plurality of fins are formed on a semiconductor substrate. A gate region is formed over a portion of the fins. The gate region comprises a first dummy gate and a second dummy gate. A gate cut region is formed over the first dummy gate. A conformal fill material is deposited into the gate cut region. At least one subsequent processing step is performed.

Methods, apparatus and system for a self-aligned gate cut on a semiconductor device

The present disclosure generally relates to semiconductor structures and, more particularly, to gate cut structures and methods of manufacture. The structure includes: a plurality of gate structures comprising source and drain regions and sidewall spacers comprised of different dielectric materials; and contacts connecting to the source and drain regions and isolated from the gate structures by the different dielectric materials.

Gate cut structures

An integrated circuit (IC) includes an active area including at least one active fin-type field effect transistor (FinFET), and a trench isolation adjacent to the active area. At least one inactive gate is positioned over the trench isolation. A vertically extending resistor body is positioned adjacent the at least one inactive gate over the trench isolation. A lower end of the resistor is below an upper surface of the trench isolation. The resistor reduces interconnect layer thickness to improve yield, and significantly reduces resistor footprint to enable scaling.

Vertical resistor adjacent inactive gate over trench isolation

One integrated circuit product disclosed herein includes a first final gate structure for a first transistor device, a second final gate structure for a second transistor device, wherein the first and second transistor devices have a gate width that extends in a gate width direction and a gate length that extends in a gate length direction, and a gate separation structure positioned between the first and second final gate structures, the gate separation structure comprising at least one insulating material. The gate separation structure further has a substantially uniform width in the gate width direction for substantially an entire vertical height of the gate separation structure and a first side surface and a second side surface, wherein an end surface of the first final gate structure contacts the first side surface and an end surface of the second final gate structure contacts the second side surface.

Insulating gate separation structure for transistor devices

The disclosure relates to methods of forming integrated circuit (IC) structures with a metal cap on a cobalt layer for source and drain regions of a transistor. An integrated circuit (IC) structure according to the disclosure may include: a semiconductor fin on a substrate; a gate structure over the substrate, the gate structure having a first portion extending transversely across the semiconductor fin; an insulator cap positioned on the gate structure above the semiconductor fin; a cobalt (Co) layer on the semiconductor fin adjacent to the gate structure, wherein an upper surface of the Co layer is below an upper surface of the gate structure; and a metal cap on the Co layer.

IC structure with metal cap on cobalt layer and methods of forming same

Processes form integrated circuit apparatuses that include parallel fins, wherein the fins are patterned in a first direction. Parallel gate structures intersect the fins in a second direction perpendicular to the first direction, wherein the gate structures have a lower portion adjacent to the fins and an upper portion distal to the fins. Source/drain structures are positioned on the fins between the gate structures. Source/drain contacts are positioned on the source/drain structures and multiple insulator layers are positioned between the gate structures and the source/drain contacts. Additional upper sidewall spacers are positioned between the upper portion of the gate structures and the multiple insulator layers.

FinFET having insulating layers between gate and source/drain contacts

This disclosure is directed to an integrated circuit (IC) structure. The IC structure may include a semiconductor substrate having a first fin and a second fin spaced from the first fin; a first source/drain region in the first fin, the first source/drain region encompassing a top surface and two opposing lateral sides of the first fin; a second source/drain region in the second fin, the second source/drain encompassing a top surface and two opposing lateral sides of the second fin; and a metal contact extending over the first source/drain region and the second source/drain region and surrounding the top surface and at least a portion of the two opposing lateral sides of each of the first and the second source/drain regions.

Wraparound contact surrounding source/drain regions of integrated circuit structures and method of forming same

Methods of forming cross-coupling contacts for field-effect transistors and structures for field effect-transistors that include cross-coupling contacts. A dielectric cap is formed over a gate structure and a sidewall spacer adjacent to a sidewall of the gate structure. A portion of the dielectric cap is removed from over the sidewall spacer and the gate structure to expose a first portion of the gate electrode of the gate structure at a top surface of the gate structure. The sidewall spacer is then recessed relative to the gate structure to expose a portion of the gate dielectric layer at the sidewall of the gate structure, which is removed to expose a second portion of the gate electrode of the gate structure. A cross-coupling contact is formed that connects the first and second portions of the gate electrode of the gate structure with an epitaxial semiconductor layer adjacent to the sidewall spacer.

Integrated gate contact and cross-coupling contact formation

A method of forming a gate cut isolation, a related structure and IC are disclosed. The method forms a dummy gate material mandrel having a sidewall positioned between and spaced from a first active region covered by the mandrel and a second active region not covered by the mandrel. A gate cut dielectric layer is formed against the sidewall of the mandrel, and may be trimmed. A dummy gate material may deposited to encase the remaining gate cut dielectric layer. Subsequent dummy gate formation and replacement metal gate processing forms a gate conductor with the gate cut isolation electrically isolating respective first and second portions of the gate conductor. The method creates a very thin, slightly non-vertical gate cut isolation, and eliminates the need to define a gate cut critical dimension or fill a small gate cut opening.

Gate cut isolation formed as layer against sidewall of dummy gate mandrel

Methods of forming a structure that includes field-effect transistor and structures that include a field effect-transistor. A dielectric cap is formed over a gate structure of a field-effect transistor, and an opening is patterned that extends fully through the dielectric cap to divide the dielectric cap into a first section and a second section spaced across the opening from the first surface. First and second dielectric spacers are respectively selectively deposited on respective first and second surfaces of the first and second sections of the dielectric cap to shorten the opening. A portion of the gate structure exposed through the opening between the first and second dielectric spacers is etched to form a cut that divides the gate electrode into first and second sections disconnected by the cut. A dielectric material is deposited in the opening and in the cut to form a dielectric pillar.

Late gate cut using selective dielectric deposition

In conjunction with a replacement metal gate (RMG) process for forming a fin field effect transistor (FinFET), gate isolation methods and associated structures leverage the formation of distinct narrow and wide gate cut regions in a sacrificial gate. The formation of a narrow gate cut between closely-spaced fins can decrease the extent of etch damage to interlayer dielectric layers located adjacent to the narrow gate cut by delaying the deposition of such dielectric layers until after formation of the narrow gate cut opening. The methods and resulting structures also decrease the propensity for short circuits between later-formed, adjacent gates.

Method of manufacturing finfet devices using narrow and wide gate cut openings in conjunction with a replacement metal gate process

A methodology for forming a fin field effect transistor (FinFET) includes the co-integration of various isolation structures, including gate cut and shallow diffusion break isolation structures that are formed with common masking and etching steps. Following an additional patterning step to provide segmentation for source/drain conductive contacts, a single deposition step is used to form an isolation dielectric layer within each of gate cut openings, shallow diffusion break openings and cavities over shallow trench isolation between device active areas.

Integrated single diffusion break

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Wappingers Falls, NY, United States of America

Laertis Economikos