Motorola Corporation

L Rodney Goke

Michael G Gallup

Robert W Seaton, Jr

Terry G Lawell

Stephen G Osborn

Thomas J Tomazin

Meltin Bell

Michael F Wiles

Jason Spielman

Yee-Wei Huang

Erik L Welty

Jack R Davis

Michael G Gallup, Deceased

William C Anderson

De-Lei Lee

Micheal G Gallup

A Single Instruction Multiple Data processor apparatus for implementing algorithms using sliding window type data is shown. The implementation shifts the elements of a Destination Vector Register (406, 606) either automatically every time the destination register value is read or in response to a specific instruction (800). The shifting of the Destination Vector Register (406, 606) allows each processing element to operate on new data. As the destination vector (406, 606) elements are shifted, a new element is provided to the vector from a Source Vector Register (404, 604).

Method and apparatus for moving data in a parallel processor using

A data processing system (55) and method thereof includes one or more data processors (10). Data processor (10) is capable of performing both vector operations and scalar operations. Using a single microsequencer (22), data processor (10) is capable of executing both vector instructions and scalar instructions. Data processor (10) also has a memory circuit (14) capable of storing both vector operands and scalar operands.

Data processing system and method thereof

Method and apparatus for performing a vector skip instruction in a data

A computer-implemented method is provided for compiling software code that performs nested conditional constructs in vector data processors (10). A vector bit stack (128) to record which processing elements (16) were activated and which processing elements were deactivated during execution of a nested conditional construct. Subsequently, when an end of a first nested conditional construct is encountered, a state of the processing elements at a point in time in which the first nested conditional construct was initiated may be popped off of the vector bit stack and a second conditional construct or any other operation may be executed. Therefore, conditional constructs may be executed while ensuring the proper state of the processing elements. The compiler program effectively utilizes the vector bit stack to store prior states of each of the processing elements of the vector data processor such that the processing elements may be efficiently restored to a correct intermediate value.

Efficient stack utilization for compiling and executing nested if-else

A data processing system (55) and method thereof includes one or more data processors (10). Data processor (10) is capable of performing both vector operations and scalar operations. Using a single microsequencer (22), data processor (10) is capable of executing both vector instructions and scalar instructions. Data processor (10) also has a memory circuit (14) capable of storing both vector operands and scalar operands. The data processing system (55) includes a plurality of instructions which include and utilize an extension bit during execution. In one embodiment, a plurality of instructions, both arithmetic and non-arithmetic, use extension bits for preliminary and non-preliminary instructions in order to accommodate large data widths.

Instruction in a data processing system utilizing extension bits and

A data processor for storing vector data in multiple locations within the processor using a pointer value and a mask value. In one embodiment, a multi-entry input data register is used to receive input data to be provided to a plurality of processing elements. A pointer value is used to address the multi-entry input data register. A mask value may be used to provide the same data to a plurality of locations within the input data register.

Method and apparatus for storing vector data in multiple non-consecutive

Saturation instruction in a data processor

The present invention, which is implemented in a data processing system, includes a method for performing a fuzzy logic operation, wherein the steps are: (1) performing a rule evaluation process on a plurality of fuzzy input values, wherein one or more of the plurality of fuzzy input values has a lower limit (zero) value, and wherein the rule evaluation process (i) implements a rulebase including a plurality of rules associating a plurality of fuzzy inputs with a plurality of fuzzy outputs, (ii) results in one or more fuzzy output values, and (iii) further includes processing the one or more of the fuzzy input values having the lower limit value with respect to the rulebase, and (2) processing the fuzzy input values having a non-lower limit value with respect to the rulebase, the processing of the fuzzy input values having the non-lower limit value performed separately from the processing of the one or more of the fuzzy input values having the lower limit value. Sorting of the non-lower limit values may be performed. Sorting may be performed using an insertion sort method wherein elements of an unsorted list stored within a vector register are compared to a growing vector of sorted values, and each element from the unsorted list is then inserted into the sorted list. Alternatively, sorting may be performed by simultaneously comparing all of the elements of an unsorted list and then transferring the largest value to a second list, wherein this process is repeated for each element in the unsorted list.

Circuit and method for processing lower limit value fuzzy inputs during

Data processor for performing a comparison instruction using selective

A method for complex data movement in a multi-processor data processing system. In one embodiment, the multi-processor data processing system (10) includes an array (12) of data processors (50-65), a plurality of edge interface circuits (14,16), and a bus interface controller (22). In an alternate embodiment, multiprocessor data processing system (210) includes an array (212) of data processors (250-258), a plurality of edge interface circuits (214-217), and a bus interface controller (222). The data processing systems (10,210) are capable of performing complex data movement patterns between the processors (50-65,250-258) and the corresponding edge interface circuits (14, 16, 214-217), such as a transpose pattern, a ping-pong pattern, and a checkerboard pattern.

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Austin, TX, United States of America

L Rodney Goke