International Business Machines Corporation

Cadence Design Systems, Inc.

L Owen Farnsworth

Brion L Keller

Bernd K Koenemann

Frank O Distler

Donald Lawrence Wheater

Leendert M Huisman

Timothy J Koprowski

Glen E Richard

Pamela Sue Gillis

Leah M Pastel

Thomas Webster Bartenstein

Raymond J Rosner

Douglas C Heaberlin

Robert W Bassett

Michael L Combs

Andrew Ferko

Francis Woytowich

Thomas James Snethen

Kevin W Stanley

Edward E Horton, Iii

Vanessa Brunkhorst

Alan R Humphrey

Garrett S Christensen

A method for reducing Pin Count Test design and test that allows parametric test patterns for high pin count ASICs to be applied using low pin count testers. The same boundary scan structure used to isolate the test of internal logic to a small number of test I/O is also used to apply parametric external I/O tests to the ASIC's functional I/O. The parametric tests are banked into pin groups and applied on the same low pin count tester used for the internal logic tests.

Parametric testing for high pin count ASIC

A method and system for generating a set of scan diagnostic patterns for diagnosing fails in scan chains. The method including: (a) selecting a set of latches; (b) selecting a pattern from a set of test patterns; (c) determining the number of lateral insertions of the selected pattern; (d) determining a number of new lateral insertions that the selected pattern would add to the set of scan diagnostic pattern and adding the selected pattern and a corresponding new insertion count to a count list; (e) repeating steps (b) through (d) until all patterns of the set of test patterns have been selected; (f) selecting a pattern from the count list; (g) adding the pattern selected from the count list to the set of scan diagnostic patterns; and (h) repeating steps (b) through (g) until a there are a predetermined number of patterns in the set of scan diagnostic patterns.

Method for optimizing a set of scan diagnostic patterns

A method of testing a semiconductor device having a memory is disclosed. The method includes selecting a portion of the memory; testing the selected portion of the memory; designating the selected portion of the memory as a designated memory in response to an acceptable testing result; and storing data in the designated portion of the memory for retrieval at a later time. Provision for soft repair of the selected memory is made. Test data can be compressed before being stored in the designated memory.

Internal cache for on chip test data storage

A system for reducing test data volume in the testing of logic products such as modules on integrated circuit chips, and systems comprised of multiple integrated circuit chips. Test stimulus data are loaded from a tester into the logic product to apply to portions of combinational logic circuitry therein in order to detect faults comprises &ldquo;care&rdquo; bits and &ldquo;non-care&rdquo; bits. The care bits target focal faults of interest in the logic circuitry being tested while the non-care bits do not. Non-care bits in the test vector data are filled with repetitive, repeating, or other background data sequences. The background data sequences are constructed such that they can be algorithmically recovered from a small amount of initialization data. The recovery can use hardware that is located in the product under test, inside the tester, or between the product under test and the tester, or software residing in the tester and operating while the test is performed. The software and/or hardware recover the full test input stimulus data including the fill data from the much more compact source data. The use of a compacted data format for the fill data provides for a high degree of compressibility of the total test input stimulus vector data set. The method for test data reduction combines the compact data representation for the input stimulus data with on-product or off-product compression of the test response data. The response data compression can be accomplished by the use of error-detecting codes, by comparing the responses from several identical products under test. The combination of data compression techniques for both, test input stimulus data and test output response data, results in significantly better overall data reduction.

System for reducing test data volume in the testing of logic products

Deterministic random Logic Built In Self Test (LBIST) is disclosed that applies Deterministic Stored Pattern Tests (DSPTs) by using random LBIST. Basically, the present invention selects the appropriate pseudorandom pattern for use with a scan cycle that needs care bits. The scan cycle may be a current or future scan cycle. In particular, the present invention determines care bits for a particular scan cycle. A pseudorandom pattern is generated that is then aligned with the particular scan cycle. If the pseudorandom pattern contains the care bits, with the correct values and in the proper positions within the pattern, this alignment tests one or more logic devices.

Deterministic random LBIST

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Lincoln, VT, United States of America

L Owen Farnsworth