Motorola Corporation

L J Reed

Philip Alan Jeffery

Harold L Spangler

A multiplexer comprises a select circuit having a plurality of OR gates responsive to digital select signals. Transistors within the OR gates are collector dotted and provide a plurality of select circuit outputs to a plurality of AND gates which are also responsive to a plurality of input signals. The collector dotting of the four OR gates of the select circuit provides a multiplexer having a single gate delay of data transmission. The multiplexer consumes less current by having only a single current source for the AND gates.

Output multiplexer having one gate delay

A digital frequency synthesizer includes a phase locked loop having dual presetting means for enabling the loop to generate a first frequency signal (e.g., 'transmit' signal) for each of many selectable channels and generate a second frequency signal (e.g., 'receiver' signal) in the form of the first frequency signal set off by an intermediate frequency (e.g., IF frequency) and programmable means for varying the frequency offset.

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Mesa, AZ, United States of America

L J Reed