National Semiconductor Corporation

Texas Instruments Corporation

Kyuwoon Hwang

Peter J Hopper

Peter B Johnson

Robert Drury

Michael Mian

Philipp Lindorfer

Andrei Papou

William David French

Vladislav Vashchenko

Peter Smeys

Andy Strachan

Ann Gabrys

Rob Drury

In a SOI process, a high lateral voltage isolation structure is formed by providing at least two concentric dielectric filled trenches, removing the semiconductor material between the dielectric filled trenches and filling the resultant gap with dielectric material to define a single wide dielectric filled trench.

Method of forming high lateral voltage isolation structure involving two separate trench fills

An apparatus and method for wafer level fabrication of high value inductors directly on top of semiconductor integrated circuits. The apparatus and method includes fabricating a semiconductor wafer including a plurality of dice, each of the dice including power circuitry and a switching node. Once the wafer is fabricated, then a plurality of inductors are fabricated directly onto the plurality of dice on the wafer respectively. Each inductor is fabricated by forming a plurality of magnetic core inductor members on an interconnect dielectric layer formed on the wafer. An insulating layer, and then inductor coils, are then formed over the plurality of magnetic core inductor members over each die. A plated magnetic layer is formed over the plurality of inductors respectively to raise the permeability and inductance of the structure.

Apparatus and method for wafer level fabrication of high value inductors on semiconductor integrated circuits

A photodetector detects the absence or presence of light by detecting a change in the inductance of a coil. The magnetic field generated when a current flows through the coil passes through an electron-hole generation region. Charged particles in the electron-hole generation region come under the influence of the magnetic field, and generate eddy currents whose magnitudes depend on whether light is absent or present. The eddy currents generate a magnetic field that opposes the magnetic field generated by current flowing through the coil.

Inductively coupled photodetector and method of forming an inductively coupled photodetector

The radio frequency (RF) impedance of a metal trace at gigahertz frequencies is reduced by forming the metal trace to have a base region and a number of fins that extend away from the base region. When formed in a spiral configuration having a number of loops, the metal trace forms an inductor with an increased quality factor (Q).

Conductive trace with reduced RF impedance resulting from the skin effect

Methods for forming multiple inductors on a semiconductor wafer are described. A plating layer and a photoresist layer are applied over a semiconductor wafer. Recess regions are etched in the photoresist layer using photolithographic techniques, which exposes portions of the underlying plating layer. Metal is electroplated into the recess regions in the photoresist layer to form multiple magnetic core inductor members. A dielectric insulating layer is applied over the magnetic core inductor members. Additional plating and photoresist layers are applied over the dielectric insulating layer. Recess regions are formed in the newly applied photoresist layer. Electroplating is used to form inductor windings in the recess regions. Optionally, a magnetic paste can be applied over the inductor coils.

An on-chip inductor structure for a DC-DC power regulator circuit merges the switching transistor metallization with the inductor. Thick top level conductor metal that is used to strap the transistor array and to lower its on-state resistance is also used to extend the power inductor into the transistor array. Thus, the structure includes three basic components: a power inductor that spirals around the transistor array, the transistor array itself, and the transistor array metallization that is used to form a distributed inductance situated over the transistor array.

On-chip power inductor

In an on-chip transformer, external electromagnetic field influences are reduced by providing an isolation transformer having primary and secondary windings with aconfiguration so that current induced by an external magnetic field is nulled.

Transformer with signal immunity to external magnetic fields

A micro-electromechanical system (MEMS) inductor is formed in a saucer shape that completely surrounds a magnetic core structure which is formed from a ferromagnetic material. In addition, an array of MEMS inductors can be formed by dividing up the saucer-shaped MEMS inductor into a number of electrically-isolated MEMS inductor wedges.

Method of forming a saucer-shaped half-loop MEMS inductor with very low resistance

An apparatus and method for wafer level fabrication of high value inductors directly on top of semiconductor integrated circuits. The apparatus and method includes fabricating a semiconductor wafer including a plurality of dice, each of the dice including power circuitry. Once the wafer is fabricated, then a plurality of inductors are fabricated directly onto the plurality of dice on the wafer and are in electrical contact with a switching node of the power circuitry on each die respectively. The inductors are fabricated by forming a plurality of magnetic core inductor members on an interconnect dielectric layer for each die on the wafer. An insulating layer and then inductor coils are then formed over the plurality of magnetic core inductor members over each die. A layer of magnetic paste is also optionally provided over each inductor coil to further increase inductance.

An apparatus and method for fabricating high value inductors embedded on semiconductor integrated circuit. The apparatus and method involve forming a conductor on the semiconductor substrate. Once the conductor is formed, a polymer material is provided on the substrate surrounding the conductor. The polymer material contains a ferromagnetic material so that the permeability of the polymer is greater than one. In various embodiments, the ferromagnetic material may be any one of a number of different high permeable materials such as iron oxide, zinc, manganese, zirconium, samarium (SA), neodymium (NA), cobalt, nickel or a combination thereof.

High value inductor with conductor surrounded by high permeability polymer formed on a semiconductor substrate

A method for determining consistency of a permeability of a ferromagnetic material in integrated circuits in which a test strip of the subject ferromagnetic material is included for testing with an impedance measurement instrument, such as an inductance-capacitance-resistance (LCR) meter, with which the resistance of the strip of ferromagnetic material over a range of measurement signal frequencies is determined based upon the measured impedance values. The measured impedance values, measurement signal frequencies and selected permeability values are then used in numerical simulations to produce multiple resistance versus frequency curves each of which corresponds to one of the selected permeability values.

Method for measuring permeability of a ferromagnetic material in an integrated circuit

A very, very low resistance micro-electromechanical system (MEMS) inductor, which provides resistance in the single-digit milliohm range, is formed by utilizing a single thick wide loop of metal formed around a magnetic core structure. The magnetic core structure, in turn, can utilize a laminated Ni&#x2014;Fe structure that has an easy axis and a hard axis.

Method of forming a MEMS inductor with very low resistance

An on-chip inductor structure includes top and bottom metal plates that are formed to surround a conductor coil formed between the top and bottom plates, but is separated therefrom by intervening dielectric material. The top and bottom plates are preferably formed from a ferromagnetic alloy, e.g. Permalloy, and are subdivided into a plurality of space-apart segments, thereby reducing eddy currents. The number of segments is optimized based upon the process technology utilized to fabricate the structure. Preferably, a finite gap is formed between the top plate and the bottom plate, the height of the gap being chosen to adjust the total inductance of the structure.

Patterned magnetic layer on-chip inductor

A method is provided for forming the ferromagnetic core of an on-chip inductor structure. In accordance with the method, a static, permanent magnet is placed in proximity to a semiconductor wafer upon which the ferromagnetic core is being electroplated. The permanent magnet is place such that the magnetic field is orthogonal to the wafer. The 'easy' axis material is that plated parallel parallel to the magnet's field and saturates at a lower applied field. The 'hard' axis is that plated perpendicular to the applied magnetic filed and saturates later, at a higher current level. This plating approach results in optimum magnetic alignment of the ferromagnetic core so as to maximize both the field strength/magnetic flux slope and magnitude before magnetic material saturation occurs.

Growing community of inventors

Palo Alto, CA, United States of America

Kyuwoon Hwang