Silicon Image Gmbh

Nvidia Corporation

Kyutaeg Oh

Conrad Arlo Maxwell

Sunil Rao Sudhakaran

Gautam Bhatia

Eunjoo Hwang

Richard J Wilcox

A transceiver configured to communicate a burst of data bits and meta-data bits for the data bits includes data channels, auxiliary data channels, and at least one error correction channel. The transceiver includes an encoder that applies 11b7s encoding to a first number of the data bits to generate first PAM-3 symbols on some or all of the communication channels, and that applies 3b2s encoding to a second number of the data bits to generate second PAM-3 symbols on at least some of the communication channels.

Hardware-efficient PAM-3 encoder and decoder

Data bits are encoded in one or both of an eleven bit seven pulse amplitude modulated three-level (PAM-3) symbol (11b7s) format and a three bit two symbol (3b2s) format on a plurality of data channels and on an error correction channel. One or more of a cyclic redundancy check (CRC) value, a poison value, and a severity value are encoded as 11b7s and/or 3b2s PAM-3 symbols on the error correction channel.

A port multiplier dynamically determines and reports its identity based on a number of supported downstream port connections. The number of supported downstream port connections can dynamically change. The port multiplier identifies devices connected to its downstream ports, whether storage devices or other port multipliers. Based on a total number of downstream ports, the port multiplier reports its identity upstream. The upstream reporting can be to another port multiplier, or the host device if directly connected to the host device. The port multiplier receives storage address space allocation from upstream based on its reported identity, and allocates the storage address space to its downstream ports.

Multi-level port expansion for port multipliers

A mechanism for facilitating configuration of port-type Peripheral Component Interconnect Express/Serial Advanced Technology Attachment host controller architecture is described. In one embodiment, an apparatus includes a plurality of PHYs to be used as Peripheral Component Interconnect Express (PCIe) ports and Serial Advanced Technology Attachment (SATA) ports, and logic to facilitate swapping of one or more of the plurality of PHYs between being the PCIe ports and the SATA ports.

Mechanism for facilitating a configurable port-type peripheral component interconnect express/serial advanced technology attachment host controller architecture

A method, apparatus and system are provided for enhancing port multipliers. In one embodiment, a port multiplier is configured to couple a network host with port multipliers. The port multiplier includes a top port multiplier to establish and maintain communication with each of the port multipliers to communicate with the network host, and the port multipliers having intermediate port multipliers and/or bottom port multipliers. Further, network devices are in communication with the port multipliers, the port multiplier, and the network host.

Growing community of inventors

San Ramon, CA, United States of America

Kyutaeg Oh