Samsung Electronics Co., Ltd.

Lg Electronics Inc.

Snu Rdb Foundation

Kyungsoo Kim

Jinin So

Yongsuk Kwon

Jonggeon Lee

Jeonghyeon Cho

Jin Woo Jung

Kyenhee Lee

Hakseong Kim

Jongwoo Hong

Sunghyun Choi

Kwangbok Lee

Nayeon Kim

Seonik Seong

Hyukju Ryu

Heesung Kang

Kyoungwan Woo

Jinyoung Park

Jonghoon Kim

Jong-Geon Lee

Dongil Bae

Eldho Pathiyakkara Thombra Mathew

Changhee Kim

Nakjin Son

MinHo Kim

Yeon Ho Park

Jonghyun Seok

Sungman Whang

Wookhyun Kwon

Kyen-hee Lee

Sachin Suresh Upadhya

Mayuresh Jyotindra Salelkar

Kyen-Hee Lee

Ilkwon Yun

A memory module includes a device memory configured to store data and including a first memory area and a second memory area, and a controller including an accelerator circuit. The controller is configured to control the device memory, transmit a command to exclude the first memory area from the system memory map to a host processor in response to a mode change request, and modify a memory configuration register to exclude the first memory area from the memory configuration register. The accelerator circuit is configured to use the first memory area to perform an acceleration operation.

Memory module, system including the same, and operation method of memory module

A semiconductor device, includes: a substrate including active regions extending in a first direction; gate electrodes extending in a second direction, intersecting the active regions; source/drain regions disposed in regions in which the active regions are recessed; buried interconnection lines disposed in the substrate; a first lower contact plug penetrating through a portion of the substrate, and connecting at least one of the source/drain regions and at least one of the buried interconnection lines; a second lower contact plug penetrating through a portion of the substrate, and connecting at least one of the gate electrodes and at least one of the buried interconnection lines; and upper contact plugs connected to a portion of the source/drain regions and a portion of the gate electrodes, wherein upper surfaces of the first and second lower contact plugs are disposed on a level lower than a level of upper surfaces of the gate electrodes.

Semiconductor devices

Disclosed are three-dimensional semiconductor devices and their fabrication methods. The 3D semiconductor device includes a first active region on a substrate and including a lower channel pattern and a lower source/drain pattern connected to the lower channel pattern, a second active region above the first active region and including an upper channel pattern and an upper source/drain pattern connected to the upper channel pattern, at least one gate electrode on the lower and upper channel patterns, a first active contact electrically connected to the lower source/drain pattern, and a second active contact electrically connected to the upper source/drain pattern. A first central line of the lower source/drain pattern and a second central line of the upper source/drain pattern in a vertical direction are offset from each other in a first direction perpendicular to the vertical direction. The first active contact and the second active contact are spaced apart from each other in the first direction.

Three-dimensional semiconductor device and method of manufacturing the same

An integrated circuit semiconductor element includes: a substrate; a complementary field effect transistor (FET) (cFET) formed over the substrate and having a quadruple-gate structure, in which nano sheet stacked structures are sequentially stacked; and a planar FET having a mono-gate structure or a zebra fin FET (ZE FINFET) having a triple-gate structure, which are formed over the substrate.

Integrated circuit semiconductor element having heterogeneous gate structures and method of fabricating integrated circuit semiconductor element

A storage device includes a first semiconductor structure having a first cell area, with memory cells disposed on a first semiconductor substrate, and a first metal pad disposed above the first cell area. A second semiconductor structure has a peripheral circuit area on a second semiconductor substrate and on which peripheral circuits are disposed, a second cell area including a plurality of second memory cells, and a second metal pad bonded to the first metal pad. A third semiconductor structure includes a memory controller disposed on a third semiconductor substrate and connected to a third metal pad through a connection via penetrating through the third semiconductor substrate. A connection structure penetrates through the second semiconductor substrate and connects the memory controller to the second semiconductor structure. The memory controller controls the first and second cell areas based on a signal applied from a host through the third metal pad.

Storage device, storage system, and operation method of storage device

A semiconductor integrated circuit device including a substrate with a first element region of a P type and a second element region of an N type, a channel active region that extends in the first element region or the second element region, the channel active region including a plurality of channels, a plurality of gate lines that extend in a second direction intersecting and include a gate metal layer, and a gate insulating film in contact with the gate metal layer, a plurality of first spacers on opposite side portions of respective ones of the gate lines, and a plurality of source/drain regions that are between ones of the plurality of gate lines. The channel active region includes a first channel directly on the substrate, and a second channel spaced apart from the first channel and extends into the gate metal layer.

Semiconductor integrated circuit device and manufacturing method thereof

A semiconductor device includes an active pattern on a substrate, a source/drain pattern on the active pattern, a gate electrode on a channel pattern connected to the source/drain pattern, an active contact on the source/drain pattern, a first lower interconnection line on the active contact, a second lower interconnection line on the gate electrode, a first spacer between the gate electrode and the active contact, and a second spacer between the first spacer and the gate electrode or the active contact. The gate electrode includes an electrode body portion and an electrode protruding portion protruding from a top surface thereof and contacting the second lower interconnection line. The active contact includes a contact body portion and a contact protruding portion protruding from a top surface thereof and contacting the first lower interconnection line. A top surface of the first spacer is higher than a top surface of the second spacer.

Semiconductor device and method of fabricating the same

A static random-access memory (SRAM) device including a three-dimensional structured (3DS) field-effect transistor (FET) having a minimized planar area and a simple wiring connection structure includes a semiconductor substrate, a first fin active region extending on the semiconductor substrate in a first direction, a second fin active region extending on the semiconductor substrate in the first direction and apart from the first fin active region in a second direction perpendicular to the first direction, and four gates extending in the second direction and intersecting part of the first fin active region or the second fin active region. Each of the first fin active region and the second fin active region includes a first region in which only a lower layer is arranged and a second region in which an upper layer is arranged on the lower layer.

Static random-access memory (SRAM) device including three-dimensional stacked (3DS) field-effect transistor (FET) and layout thereof

A method of operating a Near Memory Processing-Dual In-line Memory (NMP-DIMM) system, the method including: determining, by an adaptive latency module of the NMP-DIMM system, a synchronized read latency value for performing a read operation upon receiving a Multi-Purpose Register (MPR) read instruction from a host device communicatively connected with the NMP-DIMM system, wherein the MPR read instruction is received from the host device for training the NMP-DIMM system, wherein the synchronized read latency value is determined based on one or more read latency values associated with one or more memory units of the NMP-DIMM system; and synchronizing, by the adaptive latency module, one or more first type data paths and a second type data path in the NMP-DIMM system based on the determined synchronized read latency value.

Methods of operating a near memory processing-dual in-line memory module (NMP-DIMM) for performing a read operation and an adaptive latency module and a system thereof

An accelerator module includes a plurality of memories and a controller. The controller includes a plurality of memory controllers, a plurality of processing units, and a managing circuit. The plurality of memory controllers and the plurality of memories form a plurality of memory sub-channels. The plurality of processing units perform computational operations on a plurality of data stored in or read from the plurality of memories. The managing circuit redistributes tasks performed by the plurality of processing units or changes connections between the plurality of memory controllers and the plurality of processing units in response to a first memory sub-channel and a first processing unit being in a heavy-workload state.

Accelerator module and computing system including the same

A memory includes: a request register configured to receive a first signal including a requester identifier using a first protocol from a host and configured to output a first priority corresponding to the requester identifier; a checker module configured to receive a second signal including a command and a request type from the host and using a second protocol that is different than the first protocol, where the checker module is configured to receive the first priority from the request register, and where the checker module is configured to determine a second priority of the command based on the first priority and the request type; a command generator configured to generate an internal command for memory operation based on the command; and a memory controller configured to schedule the internal command in a command queue based on the second priority.

Memory device and scheduling method thereof

A memory module includes a memory substrate including a main connector and an auxiliary connector, configured to be connected to an external device; and a plurality of memory chips mounted on at least one of a first surface or a second surface of the memory substrate, wherein the main connector is disposed on one side of the memory substrate, and the auxiliary connector is disposed on the second surface of the memory substrate.

Memory module, main board, and server device

A booting method of a computing system, which includes a memory module including a processing device connected to a plurality of memory devices, including: powering up the computing system; after powering up the computing system, performing first memory training on the plurality of memory devices by the processing device in the memory module, and generating a module ready signal indicating completion of the first memory training; after powering up the computing system, performing a first booting sequence by a host device, the host device executing basic input/output system (BIOS) code of a BIOS memory included in the computing system; waiting for the module ready signal to be received from the memory module in the host device after performing the first booting sequence; and receiving the module ready signal in the host device, and performing a second booting sequence based on the module ready signal.

Booting method of computing system including memory module with processing device mounted

Memory modules and memory systems having the same are provided. A memory module may include command/address terminals, data terminals, at least one monitoring terminal, a buffer, and a plurality of semiconductor memory devices. The buffer may be configured to receive and buffer data applied through the data terminals and a command/address applied through the command/address terminals to generate buffered write data and a buffered command/address. The buffer may be configured to buffer the buffered write data and the buffered command/address to generate module data and a module command/address, and store and then transmit at least one portion of the buffered write data as monitoring data through the at least one monitoring terminal. The plurality of semiconductor memory devices may be configured to receive and store the module data in response to the module command/address.

Memory modules and memory systems having the same

A memory module includes a first memory device, a second memory device, and a processing buffer circuit that is connected to the first memory device and the second memory device (independently of each other) and a host. A processing buffer circuit is provided, which includes a processing circuit and a buffer. The processing circuit processes at least one of data received from the host, data stored in the first memory device, or data stored in the second memory device based on a processing command received from the host. The buffer is configured to store data processed by the processing circuit. The processing buffer circuit is configured to communicate with the host in compliance with a DDR SDRAM standard.

Growing community of inventors

Seoul, South Korea

Kyungsoo Kim